公开(公告)号：US20220351325A1

公开(公告)日：2022-11-03

申请号：US17749266

申请日：2022-05-20

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T1/20 ,  G06F9/46 ,  G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.

公开(公告)号：US11461959B2

公开(公告)日：2022-10-04

申请号：US16865587

申请日：2020-05-04

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer Kp ,  Jonathan Kennedy ,  Abhishek R. Appu ,  Jeffery S. Boles ,  Balaji Vembu ,  Michael Apodaca ,  Slawomir Grajewski ,  Gabor Liktor ,  David M. Cimini ,  Andrew T. Lauritzen ,  Travis T. Schluessler ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Kai Xiao ,  Ankur N. Shah ,  Altug Koker

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/30 ,  G06T15/00 ,  G06T11/40 ,  G06T17/20

Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

公开(公告)号：US11438722B2

公开(公告)日：2022-09-06

申请号：US17135850

申请日：2020-12-28

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Travis T. Schluessler ,  Prasoonkumar Surti ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  James M. Holland ,  Jeffery S. Boles ,  Jonathan Kennedy ,  Louis Feng ,  Atsuo Kuwahara ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: H04S7/00 ,  G09B21/00 ,  G06T1/20 ,  G06T15/06 ,  G06F3/01 ,  H04R1/40 ,  H04R3/00

Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

公开(公告)号：US11430082B2

公开(公告)日：2022-08-30

申请号：US17143805

申请日：2021-01-07

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  Dukhwan Kim

IPC: G06T1/20 ,  G06F9/46 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

公开(公告)号：US11409658B2

公开(公告)日：2022-08-09

申请号：US17161465

申请日：2021-01-28

Applicant: Intel Corporation

Inventor： Vikranth Vemulapalli ,  Lakshminarayanan Striramassarma ,  Mike MacPherson ,  Aravindh Anantaraman ,  Ben Ashbaugh ,  Murali Ramadoss ,  William B. Sadler ,  Jonathan Pearce ,  Scott Janus ,  Brent Insko ,  Vasanth Ranganathan ,  Kamal Sinha ,  Arthur Hunter, Jr. ,  Prasoonkumar Surti ,  Nicolas Galoppo von Borries ,  Joydeep Ray ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Altug Koker ,  Sungye Kim ,  Subramaniam Maiyuran ,  Valentin Andrei

IPC: G09G5/36 ,  G06F12/0862 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：US20220229576A1

公开(公告)日：2022-07-21

申请号：US17713670

申请日：2022-04-05

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Nilay Mistry

IPC: G06F3/06 ,  G06F12/06

Abstract: An apparatus to facilitate copying surface data is disclosed. The apparatus includes copy engine hardware to receive a command to access surface data from a source location in memory to a destination location in the memory, divide the surface data into a plurality of surface data sub-blocks, process the surface data sub-blocks to calculate virtual addresses to which accesses to the memory are to be performed and perform the memory accesses.

公开(公告)号：US11379235B2

公开(公告)日：2022-07-05

申请号：US17128972

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Feng Chen ,  Narayan Srinivasa ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Joydeep Ray ,  Nicolas C. Galoppo Von Borries ,  Prasoonkumar Surti ,  Ben J. Ashbaugh ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06T15/00 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0862 ,  G06F9/50 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.

公开(公告)号：US20220206990A1

公开(公告)日：2022-06-30

申请号：US17561427

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC: G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US11354769B2

公开(公告)日：2022-06-07

申请号：US16924895

申请日：2020-07-09

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T1/20 ,  G06F9/46 ,  G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.

公开(公告)号：US20220171710A1

公开(公告)日：2022-06-02

申请号：US17674703

申请日：2022-02-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Lakshminarayanan Striramassarma ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek R. Appu ,  Sean Coleman ,  Varghese George ,  Pattabhiraman K ,  Mike MacPherson ,  Subramaniam Maiyuran ,  ElMoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  Joydeep Ray ,  Jayakrishna P S ,  Prasoonkumar Surti

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897 ,  G06T15/06 ,  G06F12/0866

Abstract: Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.