公开(公告)号：US12224326B2

公开(公告)日：2025-02-11

申请号：US18378472

申请日：2023-10-10

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Pratik A. Patel ,  Ralph T. Troeger ,  Szuya S. Liao

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/321 ,  H01L29/08 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

Abstract: Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.

公开(公告)号：US12057494B2

公开(公告)日：2024-08-06

申请号：US17567753

申请日：2022-01-03

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak

IPC: H01L21/82 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/8221 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/78696 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673

Abstract: A first interconnect layer is bonded to a first substrate. The first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. The second device layer is revealed from the second substrate side. A first insulating layer is deposited on the revealed second device layer. A first opening is formed in the first insulating layer to expose a first portion of the second device layer. A contact region is formed on the exposed first portion of the second device layer.

公开(公告)号：US11984506B2

公开(公告)日：2024-05-14

申请号：US16912103

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Vishal Tiwari ,  Rishabh Mehandru ,  Dan S. Lavric ,  Michal Mleczko ,  Szuya S. Liao

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/7843 ,  H01L21/28176 ,  H01L29/401 ,  H01L29/513 ,  H01L29/517 ,  H01L29/0653

Abstract: Field effect transistors having field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, and methods of fabricating field effect transistors having gate dielectrics with dipole layers and having gate stressor layers, are described. In an example, an integrated circuit structure includes a semiconductor channel structure including a monocrystalline material. A gate dielectric is over the semiconductor channel structure, the gate dielectric including a high-k dielectric layer on a dipole material layer, and the dipole material layer distinct from the high-k dielectric layer. A gate electrode has a workfunction layer on the high-k dielectric layer, the workfunction layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

公开(公告)号：US20240128340A1

公开(公告)日：2024-04-18

申请号：US18396174

申请日：2023-12-26

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Glenn A. Glass ,  Anand S. Murthy ,  Rishabh Mehandru

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/28568 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.

公开(公告)号：US11935933B2

公开(公告)日：2024-03-19

申请号：US18131336

申请日：2023-04-05

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Kimin Jun

IPC: H01L27/12 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/1266 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/78 ,  H01L29/785 ,  H01L21/2254 ,  H01L21/26513 ,  H01L29/66545

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US11894262B2

公开(公告)日：2024-02-06

申请号：US18087129

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Patrick Morrow

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L21/76289 ,  H01L21/76283 ,  H01L21/823481 ,  H01L27/1211 ,  H01L21/3086 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/1037 ,  H01L29/6656

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

公开(公告)号：US11798838B2

公开(公告)日：2023-10-24

申请号：US16358520

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Rishabh Mehandru ,  Hui Jae Yoo ,  Patrick Morrow ,  Kevin Lin

IPC: H01L21/768 ,  H01L21/683 ,  H01L21/762 ,  H01L23/31 ,  H01L29/417

CPC classification number: H01L21/7682 ,  H01L21/6836 ,  H01L21/76256 ,  H01L23/3171 ,  H01L29/41775 ,  H01L2221/68381

Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11605556B2

公开(公告)日：2023-03-14

申请号：US16473902

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Patrick Morrow

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66

Abstract: Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.

公开(公告)号：US11552104B2

公开(公告)日：2023-01-10

申请号：US16279693

申请日：2019-02-19

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow ,  Kimin Jun

IPC: H01L27/12 ,  H01L21/84

Abstract: Disclosed herein are stacked transistors with dielectric between channel materials, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between channel materials of adjacent strata, and the dielectric material is surrounded by a gate dielectric.

公开(公告)号：US20220415708A1

公开(公告)日：2022-12-29

申请号：US17358903

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen Cea ,  Tahir Ghani ,  Patrick Keys ,  Aaron Lilak ,  Anand Murthy ,  Cory Weber

IPC: H01L21/768 ,  H01L29/10 ,  H01L27/088 ,  H01L25/07 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuitry comprising transistor structures with a source/drain etch stop layer to limit the depth of source and drain material relative to a channel of the transistor. A portion of a channel material layer may be etched in preparation for source and drain materials. The etch may be stopped at an etch stop layer buried between a channel material layer and an underlying planar substrate layer. The etch stop layer may have a different composition than the channel layer while retaining crystallinity of the channel layer. The source and drain etch stop layer may provide adequate etch selectivity to ensure a source and drain etch process does not punch through the etch stop layer. Following the etch process, source and drain materials may be formed, for example with an epitaxial growth process. The source and drain etch stop layer may be, for example, primarily silicon and carbon.