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    Bitcell state retention
    31.
    发明授权
    Bitcell state retention 有权

    公开(公告)号：US09666257B2

    公开(公告)日：2017-05-30

    申请号：US14696050

    申请日：2015-04-24

    Applicant: INTEL CORPORATION

    Inventor： Charles Augustine ,  Shigeki Tomishima ,  James W. Tschanz ,  Shih-Lien L. Lu

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C11/1659 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

    Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

    Apparatuses and systems for increasing a speed of removal of data stored in a memory cell
    32.
    发明授权
    Apparatuses and systems for increasing a speed of removal of data stored in a memory cell 有权
    用于增加存储在存储单元中的数据的移除速度的装置和系统

    公开(公告)号：US09558807B2

    公开(公告)日：2017-01-31

    申请号：US14748009

    申请日：2015-06-23

    Applicant: Intel Corporation

    Inventor： Shih-Lien Lu ,  Helia Naeimi ,  Shigeki Tomishima

    IPC: G11C11/24 ,  G11C5/14 ,  G11C7/00 ,  G11C11/4096 ,  G11C11/4074

    CPC classification number: G11C11/4094 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4078 ,  G11C11/4096

    Abstract: Embodiments include apparatuses, methods, and systems including a circuit which may increase a speed of removal of data stored in a memory cell. In embodiments, the circuit may include a control logic to detect a signal and a boost circuit coupled to the control logic to allow the control logic to disable an operation of the boost circuit in response to detection of the signal. A discharge device may be coupled to the boost circuit to accelerate leakage of a leakage current in response to the detection of the signal. In the embodiment, the leakage current is a leakage current of a memory cell coupled to the discharge device and acceleration of the leakage of the leakage current and the disablement of the operation of the boost circuit may increase a speed of erasure of data in the memory cell. Other embodiments may also be described and claimed.

    Abstract translation: 实施例包括包括可以增加存储在存储单元中的数据的移除速度的电路的装置，方法和系统。 在实施例中，电路可以包括用于检测信号的控制逻辑和耦合到控制逻辑的升压电路，以允许控制逻辑响应于信号的检测来禁止升压电路的操作。 放电装置可以耦合到升压电路，以响应于信号的检测而加速泄漏电流的泄漏。 在本实施例中，泄漏电流是耦合到放电装置的存储单元的泄漏电流，并且加速泄漏电流的泄漏以及升压电路的操作的禁用可能增加擦除存储器中的数据的速度 细胞。 也可以描述和要求保护其他实施例。

    Self-storing and self-restoring non-volatile static random access memory
    35.
    发明授权
    Self-storing and self-restoring non-volatile static random access memory 有权
    自存和自恢复非易失性静态随机存取存储器

    公开(公告)号：US09437298B1

    公开(公告)日：2016-09-06

    申请号：US14668896

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Shigeki Tomishima ,  Dmitri E. Nikonov ,  Elijah V. Ilya Karpov ,  Ian A. Young ,  Robert S. Chau

    IPC: G11C11/00 ,  G11C14/00 ,  G11C13/00 ,  G11C11/412 ,  G11C11/419 ,  G11C11/416 ,  G11C11/413 ,  G11C11/411

    CPC classification number: G11C14/009 ,  G11C11/4116 ,  G11C11/412 ,  G11C11/413 ,  G11C11/416 ,  G11C11/419 ,  G11C13/0097

    Abstract: An apparatus is provided which comprises: a Static Random Access Memory (SRAM) cell with at least two non-volatile (NV) resistive memory elements integrated within the SRAM cell; and first logic to self-store data stored in the SRAM cell to the at least two NV resistive memory elements. A method is provided which comprises performing a self-storing operation, when a voltage applied to a SRAM cell decreases to a threshold voltage, to store voltage states of the SRAM cell to at least two NV resistive memory elements, wherein the at least two NV resistive memory elements are integrated with the SRAM cell; and performing self-restoring operation, when the voltage applied to the SRAM cell increases to the threshold voltage, by copying data from the at least two NV resistive memory elements to storage nodes of the SRAM cell.

    Abstract translation: 提供了一种装置，其包括：具有集成在该SRAM单元内的至少两个非易失性（NV）电阻存储器元件的静态随机存取存储器（SRAM）单元; 以及将存储在SRAM单元中的数据自存储到至少两个NV电阻存储器元件的第一逻辑。 提供了一种方法，其包括当施加到SRAM单元的电压降低到阈值电压时执行自存储操作，以将SRAM单元的电压状态存储到至少两个NV电阻存储器元件，其中至少两个NV 电阻存储元件与SRAM单元集成; 以及当通过将来自所述至少两个NV电阻性存储器元件的数据复制到所述SRAM单元的存储节点的情况下，施加到所述SRAM单元的电压增加到阈值电压时，执行自恢复操作。

    INTEGRATED CIRCUIT DIE FOR EFFICIENT INCORPORATION IN A DIE STACK
    36.
    发明公开
    INTEGRATED CIRCUIT DIE FOR EFFICIENT INCORPORATION IN A DIE STACK 审中-公开

    公开(公告)号：US20230207428A1

    公开(公告)日：2023-06-29

    申请号：US17560915

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Shigeki Tomishima ,  Debendra Mallik

    IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L25/065

    CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657

    Abstract: Techniques and mechanisms for incorporating an integrated circuit (IC) die into a die stack. In an embodiment, the die comprises multiple interconnects extending vertically through the die. The multiple interconnects comprise first interconnects which participate in communications via a first channel, second interconnects which participate in communications via a second channel, and third interconnects which are locally insulated from any transmitter or receiver circuitry of the die. Along a direction within a horizontal plane, the third interconnects are in an alternating arrangement with the first interconnects and the second interconnects, wherein the first interconnects and the second interconnects are on opposite sides of a line which is orthogonal to the direction. In another embodiment, along the direction, the first interconnects are successively arranged to correspond to successively greater levels of bit significance, and the second interconnects are successively arranged to correspond to successively lesser levels of bit significance.

    Bitcell state retention
    39.
    发明授权
    Bitcell state retention 有权

    公开(公告)号：US10600462B2

    公开(公告)日：2020-03-24

    申请号：US15495936

    申请日：2017-04-24

    Applicant: INTEL CORPORATION

    Inventor： Charles Augustine ,  Shigeki Tomishima ,  James W. Tschanz ,  Shih-Lien L. Lu

    IPC: G11C11/00 ,  G11C11/16

    Abstract: In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access memory (RAM), STTRAM is described. In one embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by generating magnetic fields to compensate for stray magnetic fields which may cause bitcells of the memory to change state. In another embodiment, retention of bitcell bit value storage states in an STTRAM may be facilitated by selectively suspending access to a row of memory to temporarily terminate stray magnetic fields which may cause bitcells of the memory to change state. Other aspects are described herein.

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