公开(公告)号：US12237040B2

公开(公告)日：2025-02-25

申请号：US17468210

申请日：2021-09-07

Applicant: Intel Corporation

Inventor： Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad B. Khan ,  Sandeep K. Guliani ,  William K. Waller

IPC: G11C7/10 ,  G11C5/02 ,  G11C5/14

Abstract: A memory accessed by rows and/or by columns in which an array of bits can be physically stored in multi-bit wide columns in physically contiguous rows is provided. A multi-bit wide logical column is arranged diagonally across (M/multi-bits) physical rows and (M/multi-bits) physical columns with each of the plurality of multi-bit wide logical columns in the logical row stored in a different physical row and physical multi-bit column.

公开(公告)号：US20190227871A1

公开(公告)日：2019-07-25

申请号：US16375362

申请日：2019-04-04

Applicant: Intel Corporation

Inventor： Wei Wu ,  Rajesh Sundaram ,  Chetan Chauhan ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F11/10 ,  G06F3/06

Abstract: Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.

公开(公告)号：US11182242B2

公开(公告)日：2021-11-23

申请号：US16448126

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Wei Wu ,  Rajesh Sundaram ,  Shigeki Tomishima

IPC: G06F11/30 ,  G06F11/10 ,  G06F11/07

Abstract: Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

公开(公告)号：US11023320B2

公开(公告)日：2021-06-01

申请号：US16375362

申请日：2019-04-04

Applicant: Intel Corporation

Inventor： Wei Wu ,  Rajesh Sundaram ,  Chetan Chauhan ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/22

Abstract: Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.

公开(公告)号：US20200301828A1

公开(公告)日：2020-09-24

申请号：US16894180

申请日：2020-06-05

Applicant: Intel Corporation

Inventor： Jawad Khan ,  Chetan Chauhan ,  Rajesh Sundaram ,  Sourabh Dongaonkar ,  Sandeep Guliani ,  Dipanjan Sengupta ,  Mariano Tepper

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/40

Abstract: Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.

公开(公告)号：US20200265098A1

公开(公告)日：2020-08-20

申请号：US16870003

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson ,  Rajesh Sundaram

IPC: G06F16/903 ,  G06K9/62 ,  G06F17/16

Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

公开(公告)号：US20190266219A1

公开(公告)日：2019-08-29

申请号：US16411730

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Rajesh Sundaram ,  Richard Coulson ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F17/16 ,  G06F7/78 ,  G06F9/38 ,  G06F9/30

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

公开(公告)号：US12182455B2

公开(公告)日：2024-12-31

申请号：US18389525

申请日：2023-11-14

Applicant: Intel Corporation

Inventor： Nilesh N. Shah ,  Chetan Chauhan ,  Shigeki Tomishima ,  Nahid Hassan ,  Andrew Chaang Ling

IPC: G11C13/00 ,  G06F3/06 ,  G06N5/04

Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

公开(公告)号：US11989553B2

公开(公告)日：2024-05-21

申请号：US16867948

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F16/23 ,  G06F7/58 ,  G06F9/30 ,  G06F16/13 ,  G06F16/22 ,  G06F16/2455 ,  G06F16/9535 ,  G06F16/9538 ,  H01L27/06

CPC classification number: G06F9/3001 ,  G06F7/58 ,  G06F9/30036 ,  G06F16/137 ,  G06F16/2255 ,  H01L27/0688

Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.

公开(公告)号：US20230305709A1

公开(公告)日：2023-09-28

申请号：US18040145

申请日：2020-09-15

Applicant: Intel Corporation

Inventor： Dipanjan Sengupta ,  Mariano Tepper ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0673 ,  G06F3/0659

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.