公开(公告)号：US11776821B2

公开(公告)日：2023-10-03

申请号：US17669288

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Vipul Mehta ,  Edvin Cetegen ,  Yuying Wei ,  Sushrutha Gujjula ,  Nisha Ananthakrishnan ,  Shan Zhong

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13

CPC classification number: H01L21/563 ,  H01L21/67126 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/564 ,  H05K2201/09045

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. An encapsulant is over the protrusion of the substrate, the encapsulant extending beneath the first die, and the encapsulant extending beneath the second die.

公开(公告)号：US11282717B2

公开(公告)日：2022-03-22

申请号：US15942109

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Vipul Mehta ,  Edvin Cetegen ,  Yuying Wei ,  Sushrutha Gujjula ,  Nisha Ananthakrishnan ,  Shan Zhong

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

Abstract: A substrate protrusion is described. The substrate protrusion includes a top portion that extends in a first direction toward a gap between the first die and the second die and in a second direction parallel to the gap between the first die and the second die. The substrate protrusion also includes a base portion that is coupled to a substrate that extends underneath the first die and the second die. The substrate protrusion can enable void-free underfill.

公开(公告)号：US20250110295A1

公开(公告)日：2025-04-03

申请号：US18478077

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Saikumar Jayaraman ,  Yiqun Bai ,  Fan Fan ,  Dingying Xu

IPC: G02B6/42 ,  C09J171/02

Abstract: A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.

公开(公告)号：US20250079278A1

公开(公告)日：2025-03-06

申请号：US18460406

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Karumbu Nathan Meyyappan ,  Pooya Tadayon ,  Ziyin Lin ,  Gregory A. Stone

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: In one embodiment, an apparatus comprises a substrate with conductive contacts on a first side of the substrate and a housing coupled to the first side of the substrate. The housing defines a set of holes around the conductive contacts. The apparatus further includes Gallium-based liquid metal in each hole, with the liquid metal being in contact with the conductive contact of the hole. The apparatus further includes a passivation layer on a surface of the liquid metal in each hole, the passivation layer being on an opposite end of the hole from the conductive contact in the hole.

公开(公告)号：US20240222243A1

公开(公告)日：2024-07-04

申请号：US18091555

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16227

Abstract: An integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. A second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.

公开(公告)号：US20240219656A1

公开(公告)日：2024-07-04

申请号：US18089963

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Yiqun Bai ,  Bohan Shan ,  Kyle Jordan Arrington ,  Haobo Chen ,  Dingying Xu ,  Robert Alan May ,  Gang Duan ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02B6/42 ,  H01L23/15 ,  H01L25/16

CPC classification number: G02B6/4214 ,  H01L23/15 ,  H01L25/167 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240219654A1

公开(公告)日：2024-07-04

申请号：US18089892

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Yiqun Bai ,  Bohan Shan ,  Kyle Jordan Arrington ,  Haobo Chen ,  Dingying Xu ,  Robert Alan May ,  Gang Duan ,  Bai Nie ,  Srinivas Venkata Ramanuja Pietambaram

IPC: G02B6/42 ,  H01L25/16

CPC classification number: G02B6/4214 ,  H01L25/167

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240213169A1

公开(公告)日：2024-06-27

申请号：US18086265

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Jeremy D. Ecton ,  Brandon C. Marin

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/64 ,  H10B80/00

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5382 ,  H01L23/5386 ,  H01L23/645 ,  H10B80/00 ,  H01L24/32

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.

公开(公告)号：US20240112971A1

公开(公告)日：2024-04-04

申请号：US17957359

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Dingying Xu ,  Srinivas Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Haobo Chen ,  Kyle Arrington ,  Bohan Shan

IPC: H01L23/15 ,  H01L21/02 ,  H01L23/495

CPC classification number: H01L23/15 ,  H01L21/02354 ,  H01L23/49506

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.

公开(公告)号：US20230187850A1

公开(公告)日：2023-06-15

申请号：US17549427

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Ziyin Lin ,  Aaron Michael Garelick ,  Karumbu Meyyappan ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Taylor Rawlings ,  Jeffory L. Smalley ,  Pooya Tadayon ,  Dingying Xu

IPC: H01R3/08 ,  H01L23/498 ,  H01L23/32 ,  H01R43/00

CPC classification number: H01R3/08 ,  H01L23/49816 ,  H01L23/32 ,  H01L23/49833 ,  H01R43/005

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a socket that includes one or more liquid metal filled reservoirs. In selected examples, the electronic devices and sockets include configurations to aid in reducing ingress of moisture.