公开(公告)号：US20250125202A1

公开(公告)日：2025-04-17

申请号：US18984444

申请日：2024-12-17

Applicant: Intel Corporation

Inventor： Brandon Christian Marin ,  Whitney Bryks ,  Gang Duan ,  Jeremy Ecton ,  Jason Gamba ,  Haifa Hariri ,  Sashi Shekhar Kandanur ,  Joseph Peoples ,  Srinivas Venkata Ramanuja Pietambaram ,  Mohammad Mamunur Rahman ,  Bohan Shan ,  Joshua James Stacey ,  Hiroki Tanaka ,  Jacob Ryan Vehonsky

IPC: H01L23/15 ,  H01L23/18 ,  H01L23/498 ,  H01L23/64

Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having an opening between opposing first and second surfaces of the glass layer; an electronic component within the opening; a dielectric material within the opening between the electronic component and a sidewall of the opening; and a through-glass via including a conductive material that extends through the glass layer.

公开(公告)号：US20250112085A1

公开(公告)日：2025-04-03

申请号：US18375244

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Ziyin Lin ,  Haobo Chen ,  Yiqun Bai ,  Kyle Arrington ,  Jose Waimin ,  Ryan Carrazzone ,  Hongxia Feng ,  Dingying Xu ,  Srinivas Pietambaram ,  Minglu Liu ,  Seyyed Yahya Mousavi ,  Xinyu Li ,  Gang Duan ,  Wei Li ,  Bin Mu ,  Mohit Gupta ,  Jeremy Ecton ,  Brandon C. Marin ,  Xiaoying Guo ,  Ashay Dani

IPC: H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250105074A1

公开(公告)日：2025-03-27

申请号：US18977572

申请日：2024-12-11

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Wei Wei ,  Jose Fernando Waimin Almendares ,  Ryan Joseph Carrazzone ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Dingying Xu ,  Hongxia Feng ,  Yiqun Bai ,  Hiroki Tanaka ,  Brandon Christian Marin ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Gang Duan ,  Srinivas Venkata Ramanuja Pietambaram ,  Rui Zhang ,  Mohit Gupta

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

Abstract: Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.

公开(公告)号：US20240219660A1

公开(公告)日：2024-07-04

申请号：US18089934

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Eric J.M. Moret ,  Robert Alan May ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Bin Mu

IPC: G02B6/42 ,  G02B5/10

CPC classification number: G02B6/4246 ,  G02B5/10 ,  G02B6/4274

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240219655A1

公开(公告)日：2024-07-04

申请号：US18089916

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Bai Nie ,  Brandon C. Marin ,  Dingying Xu ,  Gang Duan ,  Hongxia Feng ,  Jeremy D. Ecton ,  Kristof Darmawikarta ,  Kyle Jordan Arrington ,  Srinivas Venkata Ramanuja Pietambaram ,  Xiaoying Guo ,  Yiqun Bai ,  Ziyin Lin

IPC: G02B6/42 ,  H01L21/48

CPC classification number: G02B6/4214 ,  H01L21/4803 ,  H01L23/49827

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

公开(公告)号：US20240186227A1

公开(公告)日：2024-06-06

申请号：US18061181

申请日：2022-12-02

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Kyle J. Arrington ,  Kristof Darmawikarta ,  Gang Duan ,  Jeremy D. Ecton ,  Hongxia Feng ,  Xiaoying Guo ,  Ziyin Lin ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Dingying Xu

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H05K1/0271 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4605 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/157 ,  H01L2924/15788 ,  H05K2201/0195

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.

公开(公告)号：US20230096835A1

公开(公告)日：2023-03-30

申请号：US17484519

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kyle McElhinny ,  Bohan Shan ,  Hongxia Feng ,  Xiaoying Guo ,  Adam Schmitt ,  Jacob Vehonsky ,  Steve Cho ,  Leonel Arana

IPC: H01L23/00 ,  H01L21/60 ,  H01L23/538

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

公开(公告)号：US20250112165A1

公开(公告)日：2025-04-03

申请号：US18478250

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Hiroki Tanaka ,  Robert May ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Numair Ahmed ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Bai Nie ,  Haobo Chen ,  Xiao Liu ,  Bohan Shan ,  Shruti Sharma ,  Mollie Stewart

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.

公开(公告)号：US20250105209A1

公开(公告)日：2025-03-27

申请号：US18475373

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Gang Duan ,  Yosuke Kanaoka ,  Minglu Liu ,  Srinivas V. Pietambaram ,  Brandon C. Marin ,  Bohan Shan ,  Haobo Chen ,  Jeremy Ecton ,  Benjamin T. Duong ,  Suddhasattwa Nad

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/42 ,  H01L23/538 ,  H10B80/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.

公开(公告)号：US20240264530A1

公开(公告)日：2024-08-08

申请号：US18147472

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ryan Carrazzone ,  Kyle Arrington ,  Brandon Rawlings ,  Bohan Shan ,  Dingying Xu

IPC: G03F7/16 ,  C08G75/20 ,  G03F7/038 ,  G03F7/039

CPC classification number: G03F7/168 ,  C08G75/20 ,  G03F7/038 ,  G03F7/039

Abstract: Light responsive photoresists, and methods of using light responsive photoresists in processes, such as lithography processes. The light responsive photoresists may include a polymer featuring a photocleavable group. Due to the photocleavable group, the polymer may depolymerize when irradiated with one or more wavelengths of light. The depolymerized products may be in the gas phase.