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    Memory mapped virtual doorbell mechanism
    32.
    发明授权
    Memory mapped virtual doorbell mechanism 有权

    公开(公告)号：US10831483B1

    公开(公告)日：2020-11-10

    申请号：US16397217

    申请日：2019-04-29

    Applicant: Intel Corporation

    Inventor： Bryan R. White ,  Ankur N. Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

    IPC: G06F9/30 ,  G06F12/0831 ,  G06F9/38 ,  G06F9/48 ,  G06F9/54 ,  G06F12/0837

    Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.

    Hardware assist for privilege access violation checks
    34.
    发明授权
    Hardware assist for privilege access violation checks 有权

    公开(公告)号：US10303902B2

    公开(公告)日：2019-05-28

    申请号：US15495644

    申请日：2017-04-24

    Applicant: INTEL CORPORATION

    Inventor： Hema C. Nalluri ,  Aditya Navale ,  Murali Ramadoss

    IPC: G06F21/74 ,  G06F21/84 ,  G06T15/00

    Abstract: Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU

    Hierarchical lossless compression and null data support
    35.
    发明授权
    Hierarchical lossless compression and null data support 有权

    公开(公告)号：US10282808B2

    公开(公告)日：2019-05-07

    申请号：US15167987

    申请日：2016-05-27

    Applicant: Intel Corporation

    Inventor： Larry Seiler ,  Prasoonkumar Surti ,  Aditya Navale

    IPC: G06T1/20 ,  G06F3/06 ,  G06F12/1009 ,  G06T1/60

    Abstract: Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More particularly, one or more implementations described herein facilitates hierarchical lossless compression of memory with null data support for memory resources, including texture maps. More particularly still, one or more implementations described herein facilitates the use of meta-data for lossless compression and the support of null encodings for Tiled Resources. This technology also permits use of the fast-clear compression method, where meta-data specifies that the entire access should return some specified clear value.

    Method and apparatus for parallel pixel shading
    38.
    发明授权
    Method and apparatus for parallel pixel shading 有权

    公开(公告)号：US09754342B2

    公开(公告)日：2017-09-05

    申请号：US14292064

    申请日：2014-05-30

    Applicant: Intel Corporation

    Inventor： Prasoonkumar Surti ,  Aditya Navale

    IPC: G06T1/20

    CPC classification number: G06T1/20

    Abstract: An apparatus and method for identifying sub-groups of execution resources for parallel pixel processing. For example, one embodiment of a method comprises: determining X and Y coordinates for a pixel block to be processed; performing a first set of one or more modulus operations using even bits from the X and Y coordinates to generate a first intermediate result; performing a second set of one or more modulus operations using odd bits from the X and Y coordinates to generate a second intermediate result; comparing the first intermediate result and the second intermediate result to generate a final result; and using the final result to select a first set of processing resources from a set of N processing resources for processing the pixel block.

    Priority based context preemption
    39.
    发明授权
    Priority based context preemption 有权
    基于优先级的上下文抢占

    公开(公告)号：US09396032B2

    公开(公告)日：2016-07-19

    申请号：US14227692

    申请日：2014-03-27

    Applicant: Intel Corporation

    Inventor： Hema C. Nalluri ,  Aditya Navale ,  Peter L. Doyle ,  Murali Ramadoss ,  Balaji Vembu ,  Jeffery S. Boles

    IPC: G06F9/46 ,  G06F9/50 ,  G06T1/20

    CPC classification number: G06F9/5038 ,  G06T1/20

    Abstract: Methods and apparatuses may prioritize the processing of high priority and low priority contexts submitted to a processing unit through separate high priority and low priority context submission ports. According to one embodiment, submission of a context to the low priority port causes contexts in progress to be preempted, whereas submission of a context to the high priority port causes contexts in progress to be paused.

    Abstract translation: 方法和设备可以优先处理通过单独的高优先级和低优先级上下文提交端口提交给处理单元的高优先级和低优先权上下文。 根据一个实施例，向低优先级端口提交上下文导致正在进行的上下文被抢占，而向高优先级端口提交上下文导致正在进行的上下文被暂停。

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