公开(公告)号：US11810222B2

公开(公告)日：2023-11-07

申请号：US17521009

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Larry Seiler ,  Adam Z. Leibel

IPC: G06T1/20 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/005

Abstract: Systems and methods may provide for receiving a pixel shader and sending the pixel shader to shader bypass hardware if the pixel shader and a render target associated with the pixel shader satisfy a simplicity condition. In one example, the shader bypass hardware is dedicated to pixel shaders and associated render targets that satisfy the simplicity condition.

公开(公告)号：US10223809B2

公开(公告)日：2019-03-05

申请号：US15167717

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Larry Seiler

IPC: G06T9/00 ,  G06T1/20 ,  G06T1/60 ,  G06T5/00 ,  G06T15/00

Abstract: Described herein are technologies related to facilitate lossy compression for multi-sample color data of computer graphics that maximizes the apparent quality of pixels while avoiding a corresponding burden on memory and processor bandwidth.

公开(公告)号：US10019836B2

公开(公告)日：2018-07-10

申请号：US15167865

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Larry Seiler

IPC: G06T15/40 ,  G06T15/00 ,  G06T1/20

CPC classification number: G06T15/405 ,  G06T1/20 ,  G06T15/005 ,  G06T2200/04

Abstract: Described herein are technologies related to facilitate high precision and resolution of a depth (Z) buffer storage during a process of rendering 3D scenes. More particularly, during an interpolation, encoding, and/or storing processes in a graphic pipeline for rendering the 3D scenes, a particular depth (Z) plane representation is configured to support an un-normalized depth and a floating point depth formats that may be used to store Z values to the Z buffer storage.

公开(公告)号：US20170178350A1

公开(公告)日：2017-06-22

申请号：US15454125

申请日：2017-03-09

Applicant: INTEL CORPORATION

Inventor： Prosun Chatterjee ,  Larry Seiler ,  Steven Spangler

IPC: G06T7/44 ,  G06T15/04 ,  G06T1/20 ,  G06T11/40

CPC classification number: G06T7/44 ,  G06T1/20 ,  G06T11/40 ,  G06T15/04

Abstract: A method for anisotropic filtering is provided herein. The method includes computing an anisotropic filter with a major-axis and a minor-axis for a pixel to be displayed on screen-space, wherein the anisotropic filter is to be applied to corresponding MIPs on a texture map. The method includes varying the length of the major-axis of the anisotropic filter based on the angle of the major-axis of anisotropy with respect to the screen space. The method includes determining a number of texels from the texture map that are to be sampled in the anisotropic filter based on the length of the modified major-axis. The method includes determining the color of the pixel based on the texels sampled in the anisotropic filter.

公开(公告)号：US09659402B2

公开(公告)日：2017-05-23

申请号：US14751513

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Larry Seiler

IPC: G06T15/04 ,  G06T3/40 ,  G06T3/60 ,  G06T5/00 ,  G06T7/40 ,  G09G5/28 ,  H04N1/58 ,  G06T7/00 ,  G06T3/00

CPC classification number: G06T15/04 ,  G06T1/20 ,  G06T3/0093 ,  G06T3/40 ,  G06T3/60 ,  G06T5/006 ,  G06T7/13 ,  G06T7/507 ,  G06T7/90 ,  G06T2200/12 ,  G06T2207/10024

Abstract: In accordance with some embodiments, multi-sampling may be used together with texture filtering and particularly texture filtering that generally uses rectangular grids of samples. This is accomplished by performing the texture filtering before doing the resolve, while conventionally the resolve is done and then the texture filtering is done. In addition, each sample is filtered as if it were the only sample.

公开(公告)号：US10593095B2

公开(公告)日：2020-03-17

申请号：US14738700

申请日：2015-06-12

Applicant: INTEL CORPORATION

Inventor： Larry Seiler

IPC: G06T15/04 ,  G06T11/00

Abstract: A mechanism is described for facilitating increased precision in large mip-mapped stitched textures for graphics computing devices. A method of embodiments, as described herein, includes detecting a stitched texture associated with a first frame of contents associated with an application, and a first region of interest in the stitched texture, where the stitched texture includes a mip-mapped stitched texture associated with multiple mip-levels in a mip-chain. The method may further include defining, at a first mip-level, a tile offset at a position within the first region of interest, where the first mip-level corresponds to the first frame. The method may further include creating or modifying a view of the stitched texture to specify the tile offset, and rendering the stitched texture as a normal texture with a full sub-texel precision.

公开(公告)号：US10282808B2

公开(公告)日：2019-05-07

申请号：US15167987

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Larry Seiler ,  Prasoonkumar Surti ,  Aditya Navale

IPC: G06T1/20 ,  G06F3/06 ,  G06F12/1009 ,  G06T1/60

Abstract: Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More particularly, one or more implementations described herein facilitates hierarchical lossless compression of memory with null data support for memory resources, including texture maps. More particularly still, one or more implementations described herein facilitates the use of meta-data for lossless compression and the support of null encodings for Tiled Resources. This technology also permits use of the fast-clear compression method, where meta-data specifies that the entire access should return some specified clear value.

公开(公告)号：US09990748B2

公开(公告)日：2018-06-05

申请号：US14661281

申请日：2015-03-18

Applicant: Intel Corporation

Inventor： Franz P. Clarberg ,  Robert M. Toth ,  Larry Seiler

IPC: G06T15/00 ,  G06T11/40 ,  G06T15/04

CPC classification number: G06T11/40 ,  G06T15/005 ,  G06T15/04

Abstract: The adverse affects of using out-of-bounds texels for bilateral interpolation may be reduced by redefining the valid texel domain as having four corners defined at the centers of four corner texels. As a result, the texels around the periphery of the valid texture domain are partial texels, with the corner texels being one quarter of a texel and the edges being half of a texel.

公开(公告)号：US20170345122A1

公开(公告)日：2017-11-30

申请号：US15167987

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Larry Seiler ,  Prasoonkumar Surti ,  Aditya Navale

IPC: G06T1/20 ,  G06T1/60 ,  G06F12/1009 ,  G06F3/06

CPC classification number: G06T1/20 ,  G06F3/0611 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/657 ,  G06T1/60

Abstract: Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More particularly, one or more implementations described herein facilitates hierarchical lossless compression of memory with null data support for memory resources, including texture maps. More particularly still, one or more implementations described herein facilitates the use of meta-data for lossless compression and the support of null encodings for Tiled Resources. This technology also permits use of the fast-clear compression method, where meta-data specifies that the entire access should return some specified clear value.

公开(公告)号：US20170345121A1

公开(公告)日：2017-11-30

申请号：US15167902

申请日：2016-05-27

Applicant: Intel Corporation

Inventor： Larry Seiler

IPC: G06T1/20 ,  G06T11/00 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  H04N19/182 ,  H04N19/42 ,  H04N19/593 ,  H04N19/90

Abstract: Described herein are technologies related to facilitate lossless compression for multi-sample color data of computer graphics that maximizes the apparent quality of pixels while avoiding a corresponding burden on memory and processor bandwidth.