公开(公告)号：US20210335393A1

公开(公告)日：2021-10-28

申请号：US17372298

申请日：2021-07-09

Applicant: Intel Corporation

Inventor： Chong J. ZHAO ,  Shigeki TOMISHIMA ,  Kuljit S. BAINS ,  James A. McCALL ,  Dimitrios ZIAKAS

IPC: G11C5/06

Abstract: An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

公开(公告)号：US20210020224A1

公开(公告)日：2021-01-21

申请号：US17062420

申请日：2020-10-02

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Kuljit S. BAINS ,  Christopher P. MOZAK ,  James A. McCALL ,  Akshith VASANTH ,  Bill NALE

IPC: G11C11/4072 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US20200286543A1

公开(公告)日：2020-09-10

申请号：US16741368

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Christopher P. MOZAK ,  Christopher E. COX ,  Yan FU ,  Robert J. FRIAR ,  Hsien-Pao YANG

IPC: G11C11/4072 ,  G06F3/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4076 ,  G06F13/16

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

公开(公告)号：US20190392886A1

公开(公告)日：2019-12-26

申请号：US16340084

申请日：2017-10-30

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Kuljit S. BAINS ,  Christopher P. MOZAK ,  James A. McCALL ,  Akshith VASANTH ,  Bill NALE

IPC: G11C11/4072 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4076

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US20190121754A1

公开(公告)日：2019-04-25

申请号：US16028137

申请日：2018-07-05

Applicant: Intel Corporation

Inventor： Christopher P. MOZAK ,  James A. McCALL ,  Bryan K. CASPER

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1657 ,  G06F11/10 ,  G06F13/4004 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4217 ,  G06F13/4221 ,  G06F13/4234 ,  H04L25/4915 ,  Y02D10/14 ,  Y02D10/151

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

公开(公告)号：US20190045622A1

公开(公告)日：2019-02-07

申请号：US15817098

申请日：2017-11-17

Applicant: Intel Corporation

Inventor： Jun LIAO ,  Zhen ZHOU ,  James A. McCALL ,  Jong-Ru GUO ,  Xiang LI ,  Yunhui CHU ,  Zuoguo WU

IPC: H05K1/02 ,  H05K1/14

Abstract: An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.