公开(公告)号：US20200228630A1

公开(公告)日：2020-07-16

申请号：US16833448

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Karthik KUMAR ,  Dimitrios ZIAKAS ,  Mark A. SCHMISSEUR ,  Ned SMITH

IPC: H04L29/08 ,  H04L12/911 ,  H04L12/66

Abstract: A persistence service for edge architected computing systems extends current storage and memory schemes of edge resources to expose interfaces to allow an endpoint, such as an IoT device or client device, to specify criteria for achieving persistence for data stored in an edge resource. The persistence interface extends the storage and memory controllers to store data in accordance with the criteria, including determining whether a local or remote edge resource is best able to store data persistently in a manner that satisfies the criteria. The criteria include a persistence service level agreement, including a required time to persistence, cost of persistence and reliability level of persistence. Only edge resources that contain media, including storage subsystems and/or memory, capable of storing data persistently while satisfying the criteria will be permitted to service the request. The persistence service can include a discovery service to efficiently locate objects previously stored using the persistence service.

公开(公告)号：US20170249250A1

公开(公告)日：2017-08-31

申请号：US15457847

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Raj K. RAMANUJAN ,  Rajat AGARWAL ,  Kai CHENG ,  Taarinya POLEPEDDI ,  Camille C. RAAD ,  David J. ZIMMERMAN ,  Muthukumar P. SWAMINATHAN ,  Dimitrios ZIAKAS ,  Mohan J. KUMAR ,  Bassam N. COURY ,  Glenn J. HINTON

IPC: G06F12/0811 ,  G11C11/406 ,  G06F12/0895 ,  G06F12/0897 ,  G11C14/00

CPC classification number: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02D10/13

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US20190042511A1

公开(公告)日：2019-02-07

申请号：US16023047

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Murugasamy K. NACHIMUTHU ,  Mark A. SCHMISSEUR ,  Dimitrios ZIAKAS ,  Debendra DAS SHARMA ,  Mohan J. KUMAR

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/02

Abstract: An apparatus is described. The apparatus includes a non volatile memory module for insertion into a rack implemented modular computer. The non volatile memory module includes a plurality of memory controllers. The non volatile memory includes respective non-volatile random access memory coupled to each of the memory controllers. The non volatile memory module includes a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers. The incoming requests are sent by one or more CPU modules of the rack implemented modular computer. The outgoing responses are sent to the one or more CPU modules.

公开(公告)号：US20190042162A1

公开(公告)日：2019-02-07

申请号：US16104040

申请日：2018-08-16

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Suneeta SAH ,  George VERGIS ,  Dimitrios ZIAKAS ,  Bill NALE ,  Chong J. ZHAO ,  Rajat AGARWAL

IPC: G06F3/06

Abstract: A computing system is described. The computing system includes a memory controller having a double data rate memory interface. The double data rate memory interface has a first memory channel interface and a second memory channel interface. The computing system also includes a first DIMM slot and a second DIMM slot. The computing system also includes a first memory channel coupled to the first memory channel interface and the first DIMM slot, wherein the first memory channel's CA and DQ wires are not coupled to the second DIMM slot. The computing system also includes a second memory channel coupled to the second memory channel interface and the second DIMM slot, wherein the second memory channel's CA and DQ wires are not coupled to the first DIMM slot. The computing system also includes a back end memory channel that is coupled to the first and second DIMM slots.

公开(公告)号：US20220012126A1

公开(公告)日：2022-01-13

申请号：US17483536

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Duane E. GALBI ,  Wim HEIRMAN ,  Dimitrios ZIAKAS

IPC: G06F11/10 ,  G06F12/0875 ,  G06F12/12

Abstract: A translation cache and configurable error checking and correction (“ECC”) memory reduces ECC memory overhead. The translation cache supports a configurable ECC memory capable of storing a portion of a cache line, along with any ECC data, in corresponding parts of memory devices to reduce the ECC memory overhead in a memory subsystem. The corresponding parts include any same one of an upper, lower, left or right part of memory devices in a memory module, including dynamic random access memory (“DRAM”) devices in a dual inline memory module (“DIMM”).

公开(公告)号：US20190220406A1

公开(公告)日：2019-07-18

申请号：US16363992

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Raj K. RAMANUJAN ,  Rajat AGARWAL ,  Kai CHENG ,  Taarinya POLEPEDDI ,  Camille C. RAAD ,  David J. ZIMMERMAN ,  Muthukumar P. SWAMINATHAN ,  Dimitrios ZIAKAS ,  Mohan J. KUMAR ,  Bassam N. COURY ,  Glenn J. HINTON

IPC: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G11C11/406 ,  G11C14/00

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US20180095890A1

公开(公告)日：2018-04-05

申请号：US15283065

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Dimitrios ZIAKAS

IPC: G06F12/10 ,  G06F12/06

CPC classification number: G06F12/10 ,  G06F12/0284 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/0653 ,  G06F12/109 ,  G06F2212/1024 ,  G06F2212/217

Abstract: Provided are a method, apparatus, and a system in which an initiator node is configured to communicate with a target node that is coupled to a memory. At system initialization time, a memory address map of the initiator node is generated to include addresses corresponding to the memory to which the target node is coupled. The initiator node accesses the memory coupled to the target node, by using the memory address map of the initiator node.

公开(公告)号：US20210335393A1

公开(公告)日：2021-10-28

申请号：US17372298

申请日：2021-07-09

Applicant: Intel Corporation

Inventor： Chong J. ZHAO ,  Shigeki TOMISHIMA ,  Kuljit S. BAINS ,  James A. McCALL ,  Dimitrios ZIAKAS

IPC: G11C5/06

Abstract: An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

公开(公告)号：US20190251034A1

公开(公告)日：2019-08-15

申请号：US16396576

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Dimitrios ZIAKAS ,  Mark A. SCHMISSEUR ,  Kshitij A. DOSHI ,  Kimberly A. MALONE

IPC: G06F12/0888 ,  G06F12/1027 ,  G06F12/06 ,  G06N3/04 ,  G06F9/50

CPC classification number: G06F12/0888 ,  G06F9/5016 ,  G06F9/5061 ,  G06F12/0607 ,  G06F12/1027 ,  G06N3/04

Abstract: A semiconductor chip is described. The semiconductor chip includes memory address decoder logic circuitry comprising different memory address bit manipulation paths to respectively impose different memory interleaving schemes for memory accesses directed to artificial intelligence information in a memory and non artificial intelligence information in the memory. The artificial intelligence information is to be processed with artificial intelligence logic circuitry disposed locally to the memory.

公开(公告)号：US20190035729A1

公开(公告)日：2019-01-31

申请号：US16072219

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Russell S. AOKI ,  Dimitrios ZIAKAS

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/34 ,  H01L23/498

Abstract: Semiconductor packages with programmable routing pathways are disclosed. The semiconductor package may have a source trace that may be electrically coupled to two or more different electrical pathways, where any of the electrical pathways may be activated to provide an electrical connection between the source trace and one or more destination nodes. Each of the electrical pathways may have a corresponding metal well with a correspond airgap overlying the metal well, as well as corresponding heating elements. If a particular heating element is energized, the heating element may melt metal in a corresponding metal well and the molten metal may migrate by capillary action into the overlying airgap to complete an electrical connection between the source trace and a destination node.