公开(公告)号：US11955732B2

公开(公告)日：2024-04-09

申请号：US18089220

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Erkan Alpman ,  Arnaud Lucres Amadjikpe ,  Omer Asaf ,  Kameran Azadet ,  Rotem Banin ,  Miroslav Baryakh ,  Anat Bazov ,  Stefano Brenna ,  Bryan K. Casper ,  Anandaroop Chakrabarti ,  Gregory Chance ,  Debabani Choudhury ,  Emanuel Cohen ,  Claudio Da Silva ,  Sidharth Dalmia ,  Saeid Daneshgar Asl ,  Kaushik Dasgupta ,  Kunal Datta ,  Brandon Davis ,  Ofir Degani ,  Amr M. Fahim ,  Amit Freiman ,  Michael Genossar ,  Eran Gerson ,  Eyal Goldberger ,  Eshel Gordon ,  Meir Gordon ,  Josef Hagn ,  Shinwon Kang ,  Te Yu Kao ,  Noam Kogan ,  Mikko S. Komulainen ,  Igal Yehuda Kushnir ,  Saku Lahti ,  Mikko M. Lampinen ,  Naftali Landsberg ,  Wook Bong Lee ,  Run Levinger ,  Albert Molina ,  Resti Montoya Moreno ,  Tawfiq Musah ,  Nathan G. Narevsky ,  Hosein Nikopour ,  Oner Orhan ,  Georgios Palaskas ,  Stefano Pellerano ,  Ron Pongratz ,  Ashoke Ravi ,  Shmuel Ravid ,  Peter Andrew Sagazio ,  Eren Sasoglu ,  Lior Shakedd ,  Gadi Shor ,  Baljit Singh ,  Menashe Soffer ,  Ra'anan Sover ,  Shilpa Talwar ,  Nebil Tanzi ,  Moshe Teplitsky ,  Chintan S. Thakkar ,  Jayprakash Thakur ,  Avi Tsarfati ,  Yossi Tsfati ,  Marian Verhelst ,  Nir Weisman ,  Shuhei Yamada ,  Ana M. Yepes ,  Duncan Kitchin

IPC: H01Q9/04 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q5/47 ,  H01Q21/24 ,  H03L7/14 ,  H04B1/3827 ,  H04B7/0456 ,  H04B7/06 ,  H04B15/04

CPC classification number: H01Q9/0414 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q3/24 ,  H01Q5/47 ,  H01Q21/24 ,  H03L7/145 ,  H04B1/3827 ,  H04B7/0482 ,  H04B7/0639 ,  H04B15/04

Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

公开(公告)号：US11528182B2

公开(公告)日：2022-12-13

申请号：US17351288

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Martin Clara ,  Daniel Gruber ,  Christian Lindholm ,  Hundo Shin

IPC: H03M1/10 ,  H04L27/36 ,  H03M1/06 ,  H04B1/04

Abstract: An Analog-to-Digital Converter, ADC, system is provided. The ADC system comprises a plurality of ADC circuits and a first input for receiving a transmit signal of a transceiver. One ADC circuit of the plurality of ADC circuits is coupled to the first input and configured to provide first digital data based on the transmit signal. The ADC system further comprises a second input for receiving a receive signal of the transceiver. The other ADC circuits of the plurality of ADC circuits are coupled to the second input, wherein the other ADC circuits of the plurality of ADC circuits are time-interleaved and configured to provide second digital data based on the receive signal. Additionally, the ADC system comprises a first output configured to output digital feedback data based on the first digital data, and a second output configured to output digital receive data based on the second digital data.

公开(公告)号：US11038516B1

公开(公告)日：2021-06-15

申请号：US16886817

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Ramon Sanchez ,  Albert Molina ,  Martin Clara ,  Daniel Gruber ,  Matteo Camponeschi

IPC: H03M1/10 ,  H03M1/34 ,  H03M1/06

Abstract: An apparatus and method for analog-to-digital conversion. The apparatus includes a first analog-to-digital converter (ADC), a second ADC, and a calibration unit. The first ADC is configured to sample an input analog signal at a first sampling frequency. The second ADC is configured to sample the input analog signal at a second sampling frequency. The second sampling frequency is a fraction of the first sampling frequency. The calibration unit is configured to correct a distortion incurred in an output of the first ADC based on an output of the second ADC. The first ADC may be a time-interleaved ADC. The second ADC may be an extra sub-ADC of the time-interleaved ADC. The second ADC may be configured to sample the input analog signal at random sampling phases. A dithering noise may be added to the input analog signal of the second ADC. The calibration unit may be a non-linear equalizer.

公开(公告)号：US10209987B2

公开(公告)日：2019-02-19

申请号：US15495635

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Steven C. Pinault

IPC: G06F9/30 ,  G06F17/15 ,  H03H17/06 ,  H04B1/04 ,  H04L1/00 ,  H04L27/233 ,  H04B1/62 ,  H04L25/02 ,  H04L25/03 ,  G06F5/01 ,  H03M3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04L25/49 ,  H04B1/00

Abstract: Maximum likelihood bit-stream generation and detection techniques are provided using the M-algorithm and Infinite Impulse Response (IIR) filtering. The M-Algorithm is applied to a target input signal X to perform Maximum Likelihood Sequence Estimation on the target input signal X to produce a digital bit stream B, such that after filtering by an IIR filter, the produced digital stream Y produces an error signal satisfying one or more predefined requirements. The predefined requirements comprise, for example, a substantially minimum error. In an exemplary bit detection implementation, the target input signal X comprises an observed analog signal and the produced digital stream Y comprises a digitized output of a receive channel corresponding to a transmitted bit stream. In an exemplary bit stream generation implementation, the target input signal X comprises a desired transmit signal and the produced digital stream Y comprises an estimate of the desired transmit signal.

公开(公告)号：US09923595B2

公开(公告)日：2018-03-20

申请号：US15191583

申请日：2016-06-24

Applicant: Intel Corporation

Inventor： Albert Molina ,  Kameran Azadet

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04B1/62 ,  H04L27/36 ,  G06F17/50 ,  H04B1/525 ,  H04J11/00 ,  H04L5/14 ,  H03F1/32 ,  H03F3/24

CPC classification number: H04B1/62 ,  G06F17/50 ,  G06F17/5009 ,  H03F1/3241 ,  H03F3/24 ,  H04B1/525 ,  H04J11/004 ,  H04L5/1461 ,  H04L25/03012 ,  H04L25/03343 ,  H04L27/367 ,  H04L27/368

Abstract: A signal processing circuit arrangement may include a preamplifier circuit configured to map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals, extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output, and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.

公开(公告)号：US09813224B2

公开(公告)日：2017-11-07

申请号：US14255491

申请日：2014-04-17

Applicant: Intel Corporation

Inventor： Kameran Azadet

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  H04L5/14 ,  H04L25/08 ,  G06F17/50 ,  H04B1/62 ,  H04L1/00 ,  H04B1/04 ,  G06F17/15 ,  G06F9/30 ,  H04L25/03 ,  H04L27/36 ,  H04J11/00 ,  H04B1/525

CPC classification number: H04L5/1461 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/50 ,  G06F17/5009 ,  H04B1/0475 ,  H04B1/525 ,  H04B1/62 ,  H04B2001/0425 ,  H04J11/004 ,  H04L1/0043 ,  H04L25/03012 ,  H04L25/03343 ,  H04L25/08 ,  H04L27/367 ,  H04L27/368

Abstract: A digital processor, such as a vector processor or a scalar processor, is provided having an instruction set with a complex angle function. A complex angle is evaluated for an input value, x, by obtaining one or more complex angle software instructions having the input value, x, as an input; in response to at least one of the complex angle software instructions, performing the following steps: invoking at least one complex angle functional unit that implements the one or more complex angle software instructions to apply the complex angle function to the input value, x; and generating an output corresponding to the complex angle of the input value, x, using one or more multipliers of a Multiply Accumulate (MAC) unit of the digital processor, wherein the complex angle software instruction is part of an instruction set of the digital signal processor. Multiplication operations optionally employ one or more multipliers of the MAC unit of the digital processor.

公开(公告)号：US09760338B2

公开(公告)日：2017-09-12

申请号：US15187651

申请日：2016-06-20

Applicant: Intel Corporation

Inventor： Kameran Azadet

IPC: G06F5/01 ,  G06F17/15 ,  H03H17/06 ,  H04B1/04 ,  H04L1/00 ,  H04L27/233 ,  H04B1/62 ,  G06F9/30 ,  H04L25/02 ,  H04L25/03 ,  H03M3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04L25/49 ,  H04B1/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.

公开(公告)号：US09529567B2

公开(公告)日：2016-12-27

申请号：US13701397

申请日：2012-10-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Albert Molina ,  Joseph H. Othmer ,  Parakalan Venkataraghavan ,  Meng-Lin Yu ,  Joseph Williams

IPC: G06F9/30 ,  G06F5/01 ,  H04B1/04 ,  H04L1/00 ,  H04L27/233 ,  H04B1/62 ,  H04L25/02 ,  H04L25/03 ,  H03M3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04B1/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to θ; and computing a fine corrective value using a polynomial approximation.

Abstract translation: 提供了具有具有复指数函数的指令集的数字处理器。 数字处理器通过获得具有输入值x的复数指数软件指令作为输入来评估输入值x的复指数函数; 并且响应于复杂的指数软件指令：调用至少一个复数指数函数单元，其执行复指数软件指令以将复指数函数应用于输入值x; 并产生与输入值x的复指数相对应的输出。 输入值x的复数指数函数可以通过包装输入值来保持给定范围来评估; 使用查找表计算粗近似角度; 缩放粗近似角度以获得从0到θ的角度; 以及使用多项式近似计算精细校正值。

公开(公告)号：US20160308577A1

公开(公告)日：2016-10-20

申请号：US15191583

申请日：2016-06-24

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Kameran Azadet

IPC: H04B1/62 ,  H04L27/36

CPC classification number: H04B1/62 ,  G06F17/50 ,  G06F17/5009 ,  H03F1/3241 ,  H03F3/24 ,  H04B1/525 ,  H04J11/004 ,  H04L5/1461 ,  H04L25/03012 ,  H04L25/03343 ,  H04L27/367 ,  H04L27/368

Abstract: A signal processing circuit arrangement may include a preamplifier circuit configured to map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals, extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output, and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.

Abstract translation: 信号处理电路装置可以包括前置放大器电路，其被配置为将第一维输入和第二维输入映射到二维（2D）查找表的多个查找表系数的第一子集，其中第一维输入和 所述第二尺寸输入各自表示一个或多个输入信号的信号电平，从所述多个查找表系数的所述第一子集外推，以产生查找表输出，并将所述查找表输出应用于所述一个或多个输入信号以产生 用于放大器的预失真输入信号。

公开(公告)号：US09372663B2

公开(公告)日：2016-06-21

申请号：US13701369

申请日：2012-10-26

Applicant: Intel Corporation

Inventor： Kameran Azadet

IPC: H04L27/148 ,  G06F5/01 ,  H04B1/04 ,  H04L1/00 ,  H04L27/233 ,  H04B1/62 ,  G06F9/30 ,  H04L25/02 ,  H04L25/03 ,  H03M3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04B1/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.

Abstract translation: 提供了使用最大似然序列估计直接合成RF信号的方法和装置。 通过对数字RF输入信号执行最大似然序列估计来合成RF数字RF输入信号以产生数字流，使得在通过原型滤波器滤波之后，所产生的数字流产生基本上最小的误差。 基本上最小的误差包括原型滤波器的数字输出和数字RF输入信号之间的差异。 数字流基本上等于输入的数字RF信号。 数字流可以应用于模拟恢复滤波器，并且模拟恢复滤波器的输出包括近似数字RF输入信号的模拟RF信号。