公开(公告)号：US20240223229A1

公开(公告)日：2024-07-04

申请号：US18147725

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Kameran AZADET ,  Hazar YUKSEL

IPC: H04B1/04 ,  H03F3/24

CPC classification number: H04B1/0475 ,  H03F3/245 ,  H03F2200/451 ,  H04B2001/0425

Abstract: An apparatus is proposed comprising interface circuitry configured to receive a plurality of samples causing an output signal of a power amplifier. The apparatus further comprises processing circuitry configured to allocate at least one sample of the plurality of samples to a bin based on a characteristic of the at least one sample and determine whether a predistortion for samples allocated to the bin is to be updated based on a number of samples allocated to the bin.

公开(公告)号：US20230208429A1

公开(公告)日：2023-06-29

申请号：US17645785

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Kameran AZADET ,  Martin CLARA ,  Daniel GRUBER

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

公开(公告)号：US20240213993A1

公开(公告)日：2024-06-27

申请号：US18145108

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Kameran AZADET ,  Matteo CAMPONESCHI ,  Martin CLARA

IPC: H03M1/06

CPC classification number: H03M1/0604

Abstract: Provided is an apparatus for analog-to-digital conversion. The apparatus comprises a plurality of first analog-to-digital converter, ADC, cores configured to receive an analog input signal and to generate respective first digital data based on the analog input signal. Further, the apparatus comprises a second ADC core configured to receive the analog input signal and to generate second digital data based on the analog input signal. In addition, the apparatus comprises a plurality of correction circuits each coupled to a respective one of the plurality of first ADC cores, wherein the plurality of correction circuits is configured to receive the second digital data and to modify the respective first digital data based on the second digital data.

公开(公告)号：US20220345148A1

公开(公告)日：2022-10-27

申请号：US17754310

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Kameran AZADET ,  Martin CLARA ,  Hundo SHIN

IPC: H03M1/80

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter comprises a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter comprises a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells comprise a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells comprise different numbers of inverter cells. The digital-to-analog converter additionally comprises an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

公开(公告)号：US20220345144A1

公开(公告)日：2022-10-27

申请号：US17753917

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Kameran AZADET ,  Martin CLARA ,  Daniel GRUBER ,  Albert MOLINA ,  Hundo SHIN

IPC: H03M1/10 ,  G01R31/28 ,  G01R31/3187

Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

公开(公告)号：US20230198536A1

公开(公告)日：2023-06-22

申请号：US17645461

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Kameran AZADET ,  Martin CLARA

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1033 ,  H03M1/0629

Abstract: An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.

公开(公告)号：US20220345146A1

公开(公告)日：2022-10-27

申请号：US17754309

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Kameran AZADET ,  Martin CLARA ,  Matteo CAMPONESCHI ,  Christian LINDHOLM

IPC: H03M1/46

Abstract: An analog-to-digital converter comprising a plurality of sampling cells. At least one of the plurality of sampling cells comprises a capacitive element coupled to a cell output of the at least one of the plurality of sampling cells, wherein a cell output signal is provided at the cell output. The at least one of the plurality of sampling cells further comprises a first cell input for receiving an input signal to be digitized, and a second cell input for receiving a calibration signal. Additionally, the at least one of the plurality of sampling cells comprises a first switch circuit capable of selectively coupling the first cell input to the capacitive element based on a clock signal, and a second switch circuit capable of selectively coupling the second cell input to the capacitive element, wherein a size of the second switch circuit is smaller than a size of the first switch circuit.

公开(公告)号：US20210367607A1

公开(公告)日：2021-11-25

申请号：US17059495

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Kameran AZADET ,  Matteo CAMPONESCHI ,  Jose Luis CEBALLOS ,  Christian LINDHOLM

IPC: H03M1/12 ,  H03M1/10 ,  H03M1/06

Abstract: A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter- leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.

公开(公告)号：US20240214248A1

公开(公告)日：2024-06-27

申请号：US18145874

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Albert MOLINA ,  Wayne BALLANTYNE ,  Kannan RAJAMANI ,  Benjamin JANN ,  Zoran ZIVKOVIC ,  Kameran AZADET

IPC: H04L25/03

CPC classification number: H04L25/03949 ,  H04L25/0391 ,  H04L25/03961

Abstract: An apparatus for controlling an equalizer is provided. The apparatus comprises interface circuitry configured to receive at least one of an input signal and an output signal of the equalizer. The apparatus further comprises processing circuitry configured to determine at least one signal metric based on the at least one of the input signal and the output signal of the equalizer, select an operating mode of the equalizer from a plurality of different operating modes based on the determined signal metric, and control the equalizer to operate in the selected operating mode.

公开(公告)号：US20240187012A1

公开(公告)日：2024-06-06

申请号：US18553212

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Matteo CAMPONESCHI ,  Albert MOLINA ,  Kannan RAJAMANI ,  Martin CLARA

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/18

CPC classification number: H03M1/0609 ,  H03M1/1042 ,  H03M1/188

Abstract: An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.