公开(公告)号：US11222977B2

公开(公告)日：2022-01-11

申请号：US16641022

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, the structure includes an intervening diffusion barrier deposited between the n-MOS transistor and the STI region to provide dopant diffusion reduction. In some embodiments, the diffusion barrier may include silicon dioxide with carbon concentrations between 5 and 50% by atomic percentage. In some embodiments, the diffusion barrier may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) techniques to achieve a diffusion barrier thickness in the range of 1 to 5 nanometers.

公开(公告)号：US11101356B2

公开(公告)日：2021-08-24

申请号：US16641032

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.

公开(公告)号：US20210005722A1

公开(公告)日：2021-01-07

申请号：US16641032

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.

公开(公告)号：US20190189749A1

公开(公告)日：2019-06-20

申请号：US16326890

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Benjamin Chu-Kung ,  Van Le ,  Seung Hoon Sung ,  Jack Kavalieros ,  Ashish Agrawal ,  Harold Kennel ,  Siddharth Chouksey ,  Anand Murthy ,  Tahir Ghani ,  Glenn Glass ,  Cheng-Ying Huang

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L29/1079 ,  H01L21/26506 ,  H01L29/16 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66 ,  H01L29/7851

Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.