公开(公告)号：US11152461B2

公开(公告)日：2021-10-19

申请号：US15983540

申请日：2018-05-18

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Anupama Bowonder ,  Biswajeet Guha ,  Tahir Ghani ,  Stephen M. Cea ,  William Hsu ,  Szuya S Liao ,  Pratik A. Patel

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.

公开(公告)号：US10910405B2

公开(公告)日：2021-02-02

申请号：US16785986

申请日：2020-02-10

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Patrick Morrow ,  Stephen M. Cea ,  Rishabh Mehandru ,  Cory E. Weber

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/84 ,  H01L21/306

Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

公开(公告)号：US10573715B2

公开(公告)日：2020-02-25

申请号：US15775786

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Rishabh Mehandru ,  Harold W. Kennel ,  Paul B. Fischer ,  Stephen M. Cea

IPC: H01L29/10 ,  H01L23/00 ,  H01L29/78 ,  H01L23/48 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.

公开(公告)号：US20190355811A1

公开(公告)日：2019-11-21

申请号：US15983540

申请日：2018-05-18

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Anupama Bowonder ,  Biswajeet Guha ,  Tahir Ghani ,  Stephen M. Cea ,  William Hsu ,  SZUYA S. LIAO ,  PRATIK A. PATEL

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.

公开(公告)号：US10453967B2

公开(公告)日：2019-10-22

申请号：US15743575

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Szuya S. Liao ,  Stephen M. Cea

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  B82Y10/00 ,  H01L29/775

Abstract: Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers is on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions is on either side of the pair of dielectric spacers.

公开(公告)号：US10411090B2

公开(公告)日：2019-09-10

申请号：US15745417

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Cory E. Weber ,  Rishabh Mehandru ,  Stephen M. Cea

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/66

Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.

公开(公告)号：US10304946B2

公开(公告)日：2019-05-28

申请号：US15570965

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Patrick Morrow ,  Ranjith Kumar ,  Cory E. Weber ,  Seiyon Kim ,  Stephen M. Cea ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L27/11

Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.

公开(公告)号：US10304929B2

公开(公告)日：2019-05-28

申请号：US15650569

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Jack T. Kavalieros ,  Nancy Zelick ,  Been-Yih Jin ,  Markus Kuhn ,  Stephen M. Cea

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/161

Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

公开(公告)号：US09905651B2

公开(公告)日：2018-02-27

申请号：US15405182

申请日：2017-01-12

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Sansaptak Dasgupta ,  Niti Goel ,  Van H. Le ,  Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Willy Rachmady ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Harold W. Kennel ,  Stephen M. Cea ,  Robert S. Chau

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

公开(公告)号：US20170133493A1

公开(公告)日：2017-05-11

申请号：US15410548

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, JR. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10 ,  H01L29/786 ,  H01L29/165

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.