公开(公告)号：US11663777B2

公开(公告)日：2023-05-30

申请号：US16819114

申请日：2020-03-15

Applicant: Intel Corporation

Inventor： Sven Woop ,  Carsten Benthin ,  Karthik Vaidyanathan

IPC: G06T15/06 ,  G06T17/10 ,  G06T7/254 ,  G06T1/20 ,  G06T15/00 ,  G06T15/08

CPC classification number: G06T17/10 ,  G06T1/20 ,  G06T7/254 ,  G06T15/005 ,  G06T15/06 ,  G06T15/08

Abstract: Apparatus and method for processing motion blur operations. For example, one embodiment of a graphics processing apparatus comprises: a bounding volume hierarchy (BVH) generator to build a BVH comprising hierarchically-arranged BVH nodes based on input primitives, at least one BVH node comprising one or more child nodes; and motion blur processing hardware logic to determine motion values for a quantization grid based on motion values of the one or more child nodes of the at least one BVH node and to map linear bounds of each of the child nodes to the quantization grid.

公开(公告)号：US11295409B2

公开(公告)日：2022-04-05

申请号：US17097246

申请日：2020-11-13

Applicant: INTEL CORPORATION

Inventor： Carsten Benthin ,  Sven Woop ,  Ingo Wald

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/38 ,  G06T17/10 ,  G06T15/06

Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.

公开(公告)号：US11263799B2

公开(公告)日：2022-03-01

申请号：US16910434

申请日：2020-06-24

Applicant: INTEL CORPORATION

Inventor： Prasoonkumar Surti ,  Carsten Benthin ,  Karthik Vaidyanathan ,  Philip Laws ,  Scott Janus ,  Sven Woop

IPC: G06T15/00 ,  G06T15/06

Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.

公开(公告)号：US11120608B2

公开(公告)日：2021-09-14

申请号：US16145162

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Ingo Wald ,  Carsten Benthin ,  Sven Woop

IPC: G06T15/06 ,  G06T7/50 ,  G06T15/00 ,  G06T15/50 ,  G06T1/20

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

公开(公告)号：US10699465B1

公开(公告)日：2020-06-30

申请号：US16235893

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Carsten Benthin ,  Karthik Vaidyanathan ,  Philip Laws ,  Scott Janus ,  Sven Woop

IPC: G06T15/00 ,  G06T15/06

Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.

公开(公告)号：US10679403B2

公开(公告)日：2020-06-09

申请号：US15488359

申请日：2017-04-14

Applicant: Intel Corporation

Inventor： Carsten Benthin ,  Sven Woop

IPC: G06T15/06 ,  G06T17/00

Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.