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    CIRCUITRY AND METHODS FOR ACCELERATING STREAMING DATA-TRANSFORMATION OPERATIONS
    32.
    发明申请
    CIRCUITRY AND METHODS FOR ACCELERATING STREAMING DATA-TRANSFORMATION OPERATIONS 有权

    公开(公告)号：US20230100586A1

    公开(公告)日：2023-03-30

    申请号：US17484840

    申请日：2021-09-24

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Vinodh Gopal

    IPC: G06F9/48 ,  G06F9/30

    Abstract: Systems, methods, and apparatuses for accelerating streaming data-transformation operations are described. In one example, a system on a chip (SoC) includes a hardware processor core comprising a decoder circuit to decode an instruction comprising an opcode into a decoded instruction, the opcode to indicate an execution circuit is to generate a single descriptor and cause the single descriptor to be sent to an accelerator circuit coupled to the hardware processor core, and the execution circuit to execute the decoded instruction according to the opcode; and the accelerator circuit comprising a work dispatcher circuit and one or more work execution circuits to, in response to the single descriptor sent from the hardware processor core: when a field of the single descriptor is a first value, cause a single job to be sent by the work dispatcher circuit to a single work execution circuit of the one or more work execution circuits to perform an operation indicated in the single descriptor to generate an output, and when the field of the single descriptor is a second different value, cause a plurality of jobs to be sent by the work dispatcher circuit to the one or more work execution circuits to perform the operation indicated in the single descriptor to generate the output as a single stream.

    Secure address translation services using bundle access control
    35.
    发明授权
    Secure address translation services using bundle access control 有权

    公开(公告)号：US11526451B2

    公开(公告)日：2022-12-13

    申请号：US17131974

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： David Koufaty ,  Anna Trikalinou ,  Utkarsh Y. Kakaiya ,  Ravi Sahita ,  Ramya Jayaram Masti

    IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/1045

    Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes a memory device to store memory data in a plurality of physical pages shared by a plurality of devices, a first table to map each page of memory to an associated bundle identifier (ID) that identifies one or more devices having access to a page of memory, a second table to map each bundle ID to page access permissions that define access to one or more pages associated with a bundle ID and a translation agent to receive requests from the plurality of devices to perform memory operations on the memory and determine page access permissions for requests received from the plurality of devices using the first table and the second table.

    UNIFIED ADDRESS TRANSLATION FOR VIRTUALIZATION OF INPUT/OUTPUT DEVICES
    38.
    发明申请
    UNIFIED ADDRESS TRANSLATION FOR VIRTUALIZATION OF INPUT/OUTPUT DEVICES 有权

    公开(公告)号：US20210173790A1

    公开(公告)日：2021-06-10

    申请号：US16651786

    申请日：2017-12-29

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Ashok Raj ,  Kun Tian

    IPC: G06F12/1009 ,  G06F12/1081 ,  G06F12/06 ,  G06F9/455

    Abstract: Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

    VALIDATING AN IMAGE FOR A RECONFIGURABLE DEVICE
    39.
    发明申请
    VALIDATING AN IMAGE FOR A RECONFIGURABLE DEVICE 审中-公开

    公开(公告)号：US20190109593A1

    公开(公告)日：2019-04-11

    申请号：US15942919

    申请日：2018-04-02

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. Kakaiya ,  Joshua D. Fender

    IPC: H03K19/177

    CPC classification number: H03K19/17768 ,  H03K19/17728 ,  H03K19/17764

    Abstract: A device includes a reconfigurable circuit and reconfiguration logic. The reconfiguration logic is to: receive, via a policy interface, a user policy and an image policy; receive a first reconfiguration image via a first configuration interface of a plurality of configuration interfaces; validate the first configuration interface based on the user policy; validate the first reconfiguration image based on the image policy; and in response to a determination that the first configuration interface and the first reconfiguration image are both valid, reconfigure the reconfigurable circuit using the first reconfiguration image.

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