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    SEMIICONDUCTOR LAYER THICKNESS MEASURING METHOD
    31.
    发明专利
    SEMIICONDUCTOR LAYER THICKNESS MEASURING METHOD 失效

    公开(公告)号：JPS552982A

    公开(公告)日：1980-01-10

    申请号：JP7687478

    申请日：1978-06-23

    Applicant: MATSUSHITA ELECTRIC IND CO LTD

    Inventor： SUGAWA TOSHIO ,  KONUMA TAKESHI ,  ICHINOHE EISUKE

    IPC: G01B11/06 ,  G01B21/08 ,  H01L21/66

    Abstract: PURPOSE:To make it possible to conduct optical measurement of an object by turning its required region into a multi-crystal in such a manner that an insulator is formed on the required region on a base plate prior to formation of an epithaxial layer. CONSTITUTION:An insulator layer (e.g. an approimately 500Angstrom thick film 5 of SiO2) is formed on a required region on the top surface of a base plate 4 made of such a material as phosphoric silicon. And then, an n type epithaxial layer 6 is formed. At this time, although the n type epithaxial layer 6 on the region free of SiO2 film is a single (or mono) crystal, the n type epithaxial layer 7 on the SiO2 layer is to become a multi-crystal. Now, the multi-crystal n type epithaxial layer 7 is selectively removed by using a mixed solution of fluoric acid and nitric acid. And then, the SiO2 film is removed by using fluoric acid. Now, measurement is made on difference in height between thus exposed surface of the phosphoric silicon base plate 4 and the surface of the single- (or mono-) crystal n type epithaxial layer 6.

    SEMICONDUCTOR DEVICE
    32.
    发明专利
    SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPS54101666A

    公开(公告)日：1979-08-10

    申请号：JP874578

    申请日：1978-01-27

    Applicant: MATSUSHITA ELECTRIC IND CO LTD

    Inventor： KONUMA TAKESHI ,  SUGAWA TOSHIO

    IPC: H01L29/43 ,  H01L21/28

    Abstract: PURPOSE:To lower a contact resistance and reduce irregularity by using electrode materials including Ga in electrode materials by which the ohmic contact to GaAs is formed. CONSTITUTION:Au, Ge and Ga 2 are evaporated on n-type GaAs 1, which has the surface smoothed by mechanical and chemical methods and has a carrier density of n 10 cm , by the vacuum evaporation method and are subjected to heat treatment in an inactive gas atmosphere, thereby forming alloy layer 2'.

    Buildup wiring board, and its manufacturing process
    38.
    发明专利
    Buildup wiring board, and its manufacturing process 审中-公开
    BUILDUP接线板及其制造工艺

    公开(公告)号：JP2008091604A

    公开(公告)日：2008-04-17

    申请号：JP2006270388

    申请日：2006-10-02

    Applicant: Matsushita Electric Ind Co Ltd ,  松下電器産業株式会社

    Inventor： SUGAWA TOSHIO ,  ECHIGO FUMIO ,  NAKAMURA SADASHI ,  IWAZAWA AYAKO

    IPC: H05K3/46 ,  H05K3/00

    Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable buildup wiring board in which the diameter at the bottom of a via formed in a buildup layer can be made substantially uniform.
    SOLUTION: In the buildup wiring board comprising a core substrate 11 having a via 12 formed in the insulating layer and filled with conductive paste 13 for interlayer connection, and a buildup layer 14 formed at least on one side of the core substrate 11 and having a via 15 for interlayer connection, the diameter at the bottom of the via 15 formed in the buildup layer 14 is made substantially uniform.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种高度可靠的积层布线板，其中形成在堆积层中的通孔底部的直径可以基本上均匀。 解决方案：在包括具有在绝缘层中形成的通孔12并填充有用于层间连接的导电浆料13的芯基板11的堆积布线板以及形成在芯基板11的至少一侧上的堆积层14 并且具有用于层间连接的通孔15，形成在堆积层14中的通孔15的底部的直径基本上均匀。 版权所有（C）2008，JPO＆INPIT

    Buildup wiring board
    39.
    发明专利
    Buildup wiring board 审中-公开
    BUILDUP接线板

    公开(公告)号：JP2008091603A

    公开(公告)日：2008-04-17

    申请号：JP2006270387

    申请日：2006-10-02

    Applicant: Matsushita Electric Ind Co Ltd ,  松下電器産業株式会社

    Inventor： SUGAWA TOSHIO ,  ECHIGO FUMIO ,  NAKAMURA SADASHI ,  IWAZAWA AYAKO

    IPC: H05K3/46

    CPC classification number: H01L2224/16225

    Abstract: PROBLEM TO BE SOLVED: To provide a buildup wiring board exhibiting high heat dissipation properties by touching a metal layer of the through hole of a core layer to a metal layer of the via of a buildup layer. SOLUTION: In the buildup wiring board comprising a core substrate 4 having a via 2 formed in an insulating layer 1 and filled with conductive paste 3 for interlayer connection, and a buildup layer 5 formed at least on one side of the core substrate 4 and having a via 8 for interlayer connection, the via 2 filled with the conductive paste 3 for interlayer connection is formed in each insulating layer 1 of the core substrate 4, a through hole 6 penetrating all layers of the core substrate 4 is formed, and the via 8 formed in the buildup layer 5 and the through hole 6 are made contact through metal layers 7 and 9 formed, respectively. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：通过将芯层的通孔的金属层与堆积层的通孔的金属层接触来提供展现出高散热性能的堆积布线板。 解决方案：在包括具有形成在绝缘层1中并填充有用于层间连接的导电浆料3的通孔2的芯基板4的堆积布线板中，以及形成在芯基板的至少一侧上的堆积层5 如图4所示，并且具有用于层间连接的通孔8，在芯基板4的每个绝缘层1中形成填充有用于层间连接的导电浆料3的通孔2，穿过贯穿核心基板4的所有层的通孔6， 并且形成在堆积层5和通孔6中的通孔8分别通过形成的金属层7和9接触。 版权所有（C）2008，JPO＆INPIT

    Multilayer printed circuit board and method of manufacturing same
    40.
    发明专利
    Multilayer printed circuit board and method of manufacturing same 审中-公开
    多层印刷电路板及其制造方法

    公开(公告)号：JP2007129124A

    公开(公告)日：2007-05-24

    申请号：JP2005321954

    申请日：2005-11-07

    Applicant: Matsushita Electric Ind Co Ltd ,  松下電器産業株式会社

    Inventor： NAKAMURA SADASHI ,  ECHIGO FUMIO ,  HIRAI SHOGO ,  SUGAWA TOSHIO

    IPC: H05K3/46

    CPC classification number: H05K3/4614 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4658 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T156/1092 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a thin-layered multilayer circuit board by solving the problem that a conventional multilayer circuit board using a plurality of films as insulating layers connects the films together via an adhesive may lead to a case, where the adhesive affects an effort for providing a thin-layered multilayer circuit board. SOLUTION: A plurality of double-face boards 114a, 114b using films 102a, 102b are pasted together via a paste connecting layer 116, with conductive paste 126 filled and cured in through-holes 124 formed on a temporary-cured resin 120. The curing conductive paste 126 filling the through-holes 124 preformed on the paste connecting layer 116 connects second hardwire 106a and 106b electrically, thus providing a thin-layered multilayer printed circuit board without using an adhesive. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：为了通过解决使用多个膜作为绝缘层的常规多层电路板通过粘合剂将膜连接在一起的问题来提供薄层多层电路板可能导致这样的情况，其中 粘合剂影响提供薄层多层电路板的努力。 解决方案：使用膜102a，102b的多个双面板114a，114b通过糊料连接层116粘合在一起，导电浆料126填充并固化在临时固化树脂120上形成的通孔124中 填充在膏状连接层116上的通孔124的固化导电膏126电连接第二硬线106a和106b，从而提供不使用粘合剂的薄层多层印刷电路板。 版权所有（C）2007，JPO＆INPIT

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