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    DRAM WITH ARRAY EDGE REFERENCE SENSING
    31.
    发明申请
    DRAM WITH ARRAY EDGE REFERENCE SENSING 审中-公开
    具有阵列边缘参考感测的DRAM

    公开(公告)号：WO1997023875A1

    公开(公告)日：1997-07-03

    申请号：PCT/US1996020299

    申请日：1996-12-20

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  ZAGAR, Paul, S. ,  SEYYEDY, Mirmajid

    IPC: G11C07/00

    CPC classification number: G11C7/18 ,  G11C7/14 ,  G11C11/4097 ,  G11C11/4099

    Abstract: A memory circuit is described which increases the density of memory cells by including a reference circuit. The memory circuit has an open digit line architecture where sense amplifiers use two digit lines to sense data stored in the memory cells. One of the digit lines is used as a reference while the other digit line is active. A reference circuit is described which can be used to replace one of the digit lines connected to the sense amplifier circuit. The reference circuit models the electrical charateristics of a digit line by including a capacitor and a transistor, each sized to match the characteristics of a digit line.

    Abstract translation: 描述了通过包括参考电路来增加存储器单元的密度的存储器电路。 存储器电路具有开放数字线架构，其中读出放大器使用两位数字线来感测存储在存储器单元中的数据。 其中一个数字线用作参考，而另一位数字线被激活。 描述了可用于替代连接到读出放大器电路的数字线之一的参考电路。 参考电路通过包括电容器和晶体管来模拟数字线的电特性，每个电容器和晶体管的大小可匹配数字线的特性。

    CMOS CIRCUIT ESD PROTECTION USING WELL RESISTOR
    32.
    发明申请
    CMOS CIRCUIT ESD PROTECTION USING WELL RESISTOR 审中-公开
    CMOS电路使用良好的电阻器进行ESD保护

    公开(公告)号：WO1997007544A1

    公开(公告)日：1997-02-27

    申请号：PCT/US1996012817

    申请日：1996-08-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  CASPER, Stephen, L. ,  MA, Manny, K., F. ,  SHER, Joseph, C.

    IPC: H01L27/02

    CPC classification number: H01L27/0288 ,  H01L27/0266

    Abstract: A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.

    Abstract translation: 公开了一种用于提供静电放电（ESD）保护的电路。 该电路包括一对具有减小的电阻源和漏极的CMOS场效应上拉和下拉晶体管，其中分别在供电和接地总线之间形成在其外部的阱电阻器。 在ESD事件期间，阱电阻用于限制通过晶体管的电流，并且减小它们之间的电压降。

    SINGLE DEPOSITION LAYER METAL DYNAMIC RANDOM ACCESS MEMORY
    33.
    发明申请
    SINGLE DEPOSITION LAYER METAL DYNAMIC RANDOM ACCESS MEMORY 审中-公开
    单沉积层金属动态随机存取存储器

    公开(公告)号：WO1997007543A1

    公开(公告)日：1997-02-27

    申请号：PCT/US1996001183

    申请日：1996-01-26

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  CASPER, Stephen, L. ,  ALLEN, Thimothy, J. ,  DURCAN, D., Marc ,  SHIRLEY, Brian, M. ,  RHODES, Howard, E.

    IPC: H01L23/528

    CPC classification number: H01L23/528 ,  H01L2924/0002 ,  H01L2924/1815 ,  H01L2924/00

    Abstract: A 16 megabit (2 ) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

    Abstract translation: 描述了一种16兆比特（2·24））或更大密度的单沉积层金属动态随机存取存储器（DRAM）部件，其允许适用于工业标准的300ml宽SOJ（小外形J翼）封装的管芯 或TSOP（薄型，小外形封装），与先前的双金属沉积分层16兆位DRAM设计相比，速度损失很少或没有速度损失。 这是通过使用允许单个金属层信号路径的管芯架构来实现的，以及引线框架的新颖使用以去除芯片的大部分功率，从而允许较小的速度优化的DRAM。 使用单个沉积层金属导致较低的生产成本和较短的生产时间。

    METHOD OF FORMING A Ta2O5 DIELECTRIC LAYER
    34.
    发明申请
    METHOD OF FORMING A Ta2O5 DIELECTRIC LAYER 审中-公开
    形成Ta2O5介电层的方法

    公开(公告)号：WO1996036993A1

    公开(公告)日：1996-11-21

    申请号：PCT/US1996007212

    申请日：1996-05-17

    Applicant: MICRON TECHNOLOGY, INC. ,  SANDHU, Gurtej, S. ,  FAZAN, Pierre, C.

    Inventor： MICRON TECHNOLOGY, INC.

    IPC: H01L21/70

    CPC classification number: H01L28/56 ,  H01L28/40

    Abstract: A method of forming a capacitor includes: (a) providing a node to which electrical connection to a capacitor is to be made; (b) providing a first electrically conductive capacitor plate over the node; (c) chemical vapor depositing a capacitor dielectric layer of Ta2O5 over the first electrically conductive capacitor plate; and (d) providing a predominately amorphous diffusion barrier layer over the Ta2O5 dielectric layer. A capacitor construction is also disclosed. The preferred amorphous diffusion barrier layer is electrically conductive and constitutes a metal organic chemical vapor deposited TiCxNyOz, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.5, and "z" is in the range of from 0 to 0.3, with the sum of "x", "y" and "z" equalling about 1.0.

    Abstract translation: 形成电容器的方法包括：（a）提供要与电容器进行电连接的节点; （b）在所述节点上提供第一导电电容器板; （c）在第一导电电容器板上化学气相沉积Ta 2 O 5的电容器电介质层; 和（d）在Ta 2 O 5介电层上提供主要的无定形扩散阻挡层。 还公开了一种电容器结构。 优选的非晶扩散阻挡层是导电的，并且构成金属有机化学气相沉积TiC x N y O z，其中“x”在0.01至0.5的范围内，“y”在0.99至0.5的范围内，“z “在0至0.3的范围内，”x“，”y“和”z“之和等于约1.0。

    OPTIMIZATION CIRCUITRY AND CONTROL FOR A SYNCHRONOUS MEMORY DEVICE WITH PROGRAMMABLE LATENCY PERIOD
    35.
    发明申请
    OPTIMIZATION CIRCUITRY AND CONTROL FOR A SYNCHRONOUS MEMORY DEVICE WITH PROGRAMMABLE LATENCY PERIOD 审中-公开
    具有可编程时间段的同步存储器件的优化电路和控制

    公开(公告)号：WO1996029637A2

    公开(公告)日：1996-09-26

    申请号：PCT/US1996003379

    申请日：1996-03-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  ZAGAR, Paul, Stephen ,  SCHAEGER, Scott

    IPC: G06F00/00

    CPC classification number: G11C11/4082 ,  G11C7/1018 ,  G11C11/4076 ,  G11C11/4087

    Abstract: A method and apparatus for optimizing the speed path of a memory access operation in a synchronous depending upon the present latency period for the synchronous DRAM. The improved memory device compensates the time between row address latching and column address latching tRCD by delaying the presentment of the column address to compensate tRCD from the time available for column address latching to valid data-out (tAA) when tRCD is the critical parameter. Optimization circuitry reduces the amount of time available for tAA and "shifts" it to the more critical parameter tRCD, enabling the optimization or reduction of the time allocated for tRCD by compensating tRCD with the extra time available for tAA. Thus, the memory access optimization circuitry enables an optmization or reduction in the total memory access time by compensating the optimized tRCD with the extra time available for tAA.

    Abstract translation: 一种用于根据当前等时周期对同步DRAM进行同步优化存储器访问操作的速度路径的方法和装置。 改进的存储器件通过延迟列地址的呈现来补偿行地址锁存和列地址锁存tRCD之间的时间，以便当tRCD是关键参数时，从可用于列地址锁存的时间到有效数据输出（tAA）补偿tRCD。 优化电路减少了可用于tAA的时间量，并将其“移动”到更关键的参数tRCD，通过用tAA可用的额外时间补偿tRCD，可以优化或减少分配给tRCD的时间。 因此，存储器访问优化电​​路通过利用可用于tAA的额外时间来补偿优化的tRCD来实现对存储器访问总时间的优化或减少。

    BURST EDO MEMORY DEVICE
    36.
    发明申请
    BURST EDO MEMORY DEVICE 审中-公开
    BURST EDO存储设备

    公开(公告)号：WO1996020482A1

    公开(公告)日：1996-07-04

    申请号：PCT/US1995016984

    申请日：1995-12-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  ZAGAR, Paul, S. ,  WILLIAMS, Brett, L. ,  MANNING, Troy, A. ,  MERRITT, Todd, A.

    IPC: G11C07/00

    CPC classification number: G11C7/109 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/407

    Abstract: An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and intialize the device for another burst access. A two stage pipelined output buffer latches read data in a first stage while data from a second stage is driven from the device. Internal read lines may become invalid in preparation for additional access cycles after the data is latched in the first stage. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and the other memory circuit designs. The memory device maintains compatibility with nonburst mode devices such as Extended Data Out (EDO) and Fast Page Mode through bond option or mode selection circuitry. A multiplexer selects between the input address and the burst address generator output to feed an asynchronous address transition detection circuit. The address transition detection circuit generates an equilibration control signal between memory access cycles.

    Abstract translation: 集成电路存储器件被设计用于高速数据访问和与现有存储器系统的兼容性。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问的开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 突发访问期间读/写控制线的转换将终止突发访问，重置突发长度计数器，并初始化设备以进行另一个突发访问。 两级流水线输出缓冲器在第一级锁存读取数据，同时从设备驱动来自第二级的数据。 数据在第一阶段锁存后，内部读取行可能无法准备额外的访问周期。 该器件与现有的扩展数据输出DRAM器件引脚排列，快速页面模式和扩展数据输出单列直插存储器模块引脚排列以及其他存储器电路设计兼容。 存储器件通过接合选项或模式选择电路保持与非突发模式器件的兼容性，例如扩展数据输出（EDO）和快速寻呼模式。 多路复用器在输入地址和突发地址发生器输出之间选择馈送异步地址转换检测电路。 地址转换检测电路在存储器访问周期之间产生平衡控制信号。

    MULTI-LAYER LEAD FRAME FOR A SEMICONDUCTOR DEVICE
    39.
    发明申请
    MULTI-LAYER LEAD FRAME FOR A SEMICONDUCTOR DEVICE 审中-公开
    用于半导体器件的多层引线框架

    公开(公告)号：WO1996015555A1

    公开(公告)日：1996-05-23

    申请号：PCT/US1995014569

    申请日：1995-11-07

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： MICRON TECHNOLOGY, INC. ,  STAVE, Eric, J.

    IPC: H01L23/495

    CPC classification number: H01L23/49589 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    Abstract: A multi-layer lead frame (20) for decoupling a power supply to a semiconductor die (10) includes overlaying first (25) and second lead frame (40) bodies having an insulator (55) disposed therebetween and at least one main lead finger (35, 50) extending from each body (25, 40). The bodies (25, 40) act as a capacitor to decouple the power supply to the die (10). One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die (10), and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die (10). The first body (25) includes a die paddle (30) for supporting the die (10), and the second body (40) includes a plate (45) for overlaying the paddle (30) with the insulator (55) disposed between the paddle (30) and plate (45), thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.

    Abstract translation: 用于将电源去耦合到半导体管芯（10）的多层引线框架（20）包括覆盖第一（25）和第二引线框架（40）的主体，绝缘体（55）设置在它们之间，并且至少一个主引线指 （35,50），其从每个主体（25,40）延伸。 主体（25,40）用作电容器以将电源分离到管芯（10）。 主体和相应手指中的一个提供用于与模具（10）引线接合的电源和接地连接之一，并且另一个主体提供用于与模具（10）引线接合的另一个电源和接地连接。 第一主体（25）包括用于支撑模具（10）的模板（30），并且第二主体（40）包括用于将桨叶（30）与绝缘体（55）重叠的板（45） 叶片（30）和板（45），从而在分别提供电源和接地连接时在其间提供电去耦效应。

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