公开(公告)号：CA1299663C

公开(公告)日：1992-04-28

申请号：CA582390

申请日：1988-11-07

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER L

IPC: G08B5/22 ,  H04B7/26 ,  H04W8/24 ,  H04W88/02 ,  H04B1/16

Abstract: A digital selective call receiver is modified to enhance the address decoding capability by providing access to received data, bit and frame synchronization signals, and a detect input terminal of an annunciator. A selectively attachable additional independent address decoding device including additional memory and an independent address decoder operating in parallel with the decoder in the selective call receiver is attached to the receiver for accessing the various signals and providing a detect signal to the annunciator when an additional independent address is decoded.

公开(公告)号：CA1298620C

公开(公告)日：1992-04-07

申请号：CA564696

申请日：1988-04-21

Applicant: MOTOROLA INC

Inventor： FISCH KENNETH D ,  DAVIS WALTER L

IPC: H04Q7/14 ,  G08B3/10 ,  H04B1/16

Abstract: A device and method are disclosed for saving stored messages in a digital stored voice paging receiver (10). The digital stored voice paging receiver (10) includes a plurality of message slots, each slot capable of storing a digitized voice message. A status value associated with a message slot is representative of the status of the message in the slot. A first embodiment of the method stores messages in the message slots by chronologically replacing older messages. A second embodiment of the method orders the stored messages in a predetermined priority. A stored message is replaced by an incoming message when the incoming message priority status is greater than the stored message priority status.

公开(公告)号：CA2000683A1

公开(公告)日：1990-06-01

申请号：CA2000683

申请日：1989-10-13

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER L

IPC: H04B1/16 ,  H04B20060101 ,  H04W52/02 ,  H04W88/02

Abstract: A receiver (70) receives a transmitted signal having a periodic predetermined signal, a method and apparatus (99) detects a first predetermined signal. Power may be conserved during a portion of a subsequent predetermined signal. The subsequent predetermined signal is divided into at least a first and second portion. If the first portion is detected, the subsequent predetermined signal is considered detected and power is conserved for the second portion. If the first portion is not detected, the receiver remains active for the second portion in order to detect the subsequent predetermined signal.

公开(公告)号：IT1172203B

公开(公告)日：1987-06-18

申请号：IT4939981

申请日：1981-09-30

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER L ,  JACOBSON JR JAMES E

IPC: G05F1/56 ,  G05F3/20 ,  H02M3/155 ,  H02M3/156 ,  H02M3/335 ,  H02M

Abstract: A DC/DC converter operates at peak efficiency in either of two output current level states in response to the power demands of an associated electronic device, thereby reducing wasted current to a minimum. The converter is designed to operate from a one-cell battery, and is particularly suited to an integrated circuit implementation.

公开(公告)号：BR8407147A

公开(公告)日：1985-10-08

申请号：BR8407147

申请日：1984-10-30

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER L ,  HEROLD BARRY W ,  LITTLE WENDELL L

IPC: G06F1/00 ,  G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G06F15/78 ,  H03L7/089 ,  H03L7/107 ,  H03L7/183 ,  G06F7/68

Abstract: A microcomputer (104) having predetermined clock pulse frequency requirements receives pulses from a multiplying type frequency synthesizer (200) which utilizes a reference frequency less than the largest of the predetermined requirements. The synthesizer (200) is responsive to program instructions to generate clock pulse frequencies sufficient to satisfy the requirement for immediate execution of programmed tasks. As the execution requirements change, the synthesizer (200) responds to provide only the frequency required. Thus, the power dissipated by the entire microcomputer system is minimized.

公开(公告)号：CA1168371A

公开(公告)日：1984-05-29

申请号：CA384443

申请日：1981-08-24

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER L ,  JACOBSON JAMES E JR

IPC: G06F1/00 ,  G06F1/24 ,  G06F1/32 ,  G06F9/00 ,  G06F11/00 ,  G06F11/14 ,  G06F11/30 ,  H04Q7/14 ,  G06F9/22

Abstract: A dual deadman timer circuit functions to reset a dual mode microprocessor in the event of loss of program control. The microprocessor has high and low power requirements corresponding to its two operating modes, and the deadman timer circuit also adjusts the output power level of an associated two-level power supply to ensure that sufficient power is available for the full operation of the microprocessor during reset. The deadman timer functions during both microprocessor modes and includes two level-sensitive input sections to ensure that the microprocessor is reset under an error condition.

公开(公告)号：CA1149458A

公开(公告)日：1983-07-05

申请号：CA373155

申请日：1981-03-17

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER L

IPC: G05F3/16

Abstract: A highly accurate current mirror for IC implementation is comprised of low beta transistors and operates on a low supply voltage by utilizing a bias network with a balance sensing feedback network to control the bias voltage. The output current of one of the mirror transistors is compared with the reference current and the level of the current is then forced to equal the reference by means of the bias voltage adjustment.

公开(公告)号：IT8149399D0

公开(公告)日：1981-09-30

申请号：IT4939981

申请日：1981-09-30

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER L ,  JACOBSON JAMES E JR

IPC: G05F1/56 ,  G05F3/20 ,  H02M3/155 ,  H02M3/156 ,  H02M3/335 ,  H02M

Abstract: A DC/DC converter operates at peak efficiency in either of two output current level states in response to the power demands of an associated electronic device, thereby reducing wasted current to a minimum. The converter is designed to operate from a one-cell battery, and is particularly suited to an integrated circuit implementation.

公开(公告)号：EP0682835A4

公开(公告)日：1999-02-10

申请号：EP94902388

申请日：1993-11-24

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER L

IPC: H04B7/26 ,  H04M11/00 ,  H04M11/02 ,  H04W88/18

CPC classification number: H04W88/185 ,  H04M11/022

Abstract: A combination radio paging receiver and radio telephone (40) includes a receiver (214) for receiving paging signals provided from a paging terminal (32), a decoder (216) for decoding the paging sgnals to recover a page, and a controller (220) for determining whether the page requests an acknowledge back signal. A radio telephone section (205) couples the controller (220) to a radio telephone system (15) to form a radio telephone link with the paging terminal (32) for communicating the acknowledge back signal to the paging terminal (32) via the radio telephone link in response to determining that the page requests the acknowledge back signal (304).

公开(公告)号：EP0593455A4

公开(公告)日：1994-07-13

申请号：EP91906081

申请日：1991-02-11

Applicant: MOTOROLA INC

Inventor： DAVIS WALTER L

IPC: G08B15/00 ,  G08B3/10 ,  G08B25/10 ,  H04W88/02 ,  G08B5/22

CPC classification number: H04W88/022 ,  G08B3/1066

Abstract: A selective call receiver (10) capable of presenting a message comprises a receiver (12) for receiving a signal including a synchronization word (22) and a security code word (26), and a processor (16) for disabling the selective call receiver if the security code word is not received in conjunction with at least one of a predetermined number of synchronization words.