公开(公告)号：JP2013168655A

公开(公告)日：2013-08-29

申请号：JP2013041160

申请日：2013-03-01

Applicant: Nec Corp ,  日本電気株式会社

Inventor： NARITA KAORU

IPC: H01L21/822 ,  C01B31/02 ,  H01C7/00 ,  H01L21/336 ,  H01L21/82 ,  H01L27/04 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L27/0629 ,  B82Y10/00 ,  G11C13/025 ,  G11C17/16 ,  G11C17/165 ,  H01C7/006 ,  H01C17/0652 ,  H01L28/22 ,  H01L29/0665 ,  H01L29/0673 ,  H01L51/0018 ,  H01L51/0048 ,  Y10S977/961

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a high-reliability resistor or a carbon nano-tube resistor capable of applying fuse.SOLUTION: A manufacturing method includes a step for preparing an initial solution by throwing a carbon nano-tube into a volatile solvent so as to be a first concentration and applying ultrasonic processing thereto, a step for diluting the initial solution with the volatile solvent step by step while applying ultrasonic processing, adjusting the initial solution to be a second concentration and preparing a coating solution, and a step for applying the coating solution between a first electrode and a second electrode. The first concentration is a concentration equal to or higher than 1×10g/ml and the second concentration is lower than 1×10g/ml.

Abstract translation: 要解决的问题：提供一种制造能够应用熔丝的高可靠性电阻器或碳纳米管电阻器的方法。解决方案：一种制造方法包括通过将碳纳米管投入到制备初始溶液的步骤 挥发性溶剂作为第一浓度并对其进行超声处理，在施加超声波处理的同时，用挥发性溶剂稀释初始溶液的步骤，将初始溶液调节为第二浓度并制备涂布溶液， 在第一电极和第二电极之间施加涂布溶液的步骤。 第一浓度为1×10g / ml以上，第二浓度低于1×10g / ml。

公开(公告)号：JPH1187631A

公开(公告)日：1999-03-30

申请号：JP24384797

申请日：1997-09-09

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L29/78 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To protect an output transistor and an internal circuit from electrostatic breakdown with a circuit configuration of minimum pattern area. SOLUTION: Between an input/output terminal 11, which is a metal terminal for connection to an external circuit and a resistor 13 of a wiring connected to an internal circuit, an output transistor 12 which controls an electric potential of input/output signal is provided via a parasitic resistor 103. In addition, in order to protect the internal circuit and the output transistor 12 from surge current, a protective transistor 14 and a trigger diode 15 which form a discharge path are connected to the input/output terminal via a parasitic resistor 102.

公开(公告)号：JPH1050833A

公开(公告)日：1998-02-20

申请号：JP20561296

申请日：1996-08-05

Applicant: NEC CORP

Inventor： NARITA KAORU ,  FUJII TAKEO

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/62 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enable connection to each point of an impurity diffusion layer through a uniform resistance by providing a contact opening part between an impurity diffusion layer and a wiring layer of a relatively high resistance. SOLUTION: A metallic wiring 1 is connected to a tungsten silicide wiring layer by a first contact 104. The tungsten silicide wiring layer is connected to a drain diffusion layer by a second contact 105. The first contact 104 and the second contact 105 are formed alternately and a metallic wiring is connected to a drain diffusion layer 107 through a resistance of a tungsten silicide wiring layer. An excess current is applied to an input/output terminal, and even if an MOSFET switches on by bi-polar operation, it is a tungsten silicide layer of high melting point that is directly connected to the drain diffusion layer 107 and a contact is not fused. Furthermore, since a resistance of a tungsten silicide layer enters the drain diffusion layer 107 from a metallic wiring in series, discharge current flowing during excess voltage application is limited and electrostatic breakdown strength is improved.

公开(公告)号：JPH09139468A

公开(公告)日：1997-05-27

申请号：JP29655095

申请日：1995-11-15

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06

Abstract: PROBLEM TO BE SOLVED: To make small an LSI chip in size by a method wherein a dead space is reduced by connecting a resistor between an earthing conductor or a power source terminal and a protective element, or between an input/output terminal and the protective element, and the protective element and the element to be protected are arranged in close proximity with each other without lowering electrostatic breakdown withstand voltage. SOLUTION: At least one or more earth terminals or power source terminals 103, which are provided on a semiconductor substrate 100 and connected to the internal circuit, and an input/output terminal 102 are provided. The above- mentioned earth terminals or power source terminals 103 and the input/output terminal 102 are connected to a common wiring 101 through protective elements 105 and 106. In the semiconductor integrated circuit device as above-mentioned, a resistor 110 is connected between the earth terminal or the power source terminal 103 and the protective element 106, or between the input/output terminal 102 and the protective element 105. For example, the resistance value of the resistor 110 is set in such a manner that the resistance value of the wiring path, which links the earth terminal or the power source terminal 103 and the input/output terminal 102, becomes 15Ω or smaller.

公开(公告)号：JPH09116112A

公开(公告)日：1997-05-02

申请号：JP29208695

申请日：1995-10-14

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To prevent the degradation of the data holding characteristic of a semiconductor storage device, by reducing its leakage current to lengthen its data holding time. SOLUTION: On a surface insulation film 10 of a semiconductor substrate 1 of one conduction type, a polycrystal silicon film 11 is formed, providing an opening portion 13 therein to expose the semiconductor substrate 1 to the external, and by a side wall 12 provided on the inner wall of the opening portion 13 the polycrystal silicon film 11 and the semiconductor substrate 1 are connected. A gate insulation film 4 plus a gate electrode 3 and source.drain regions 11S, 11D of the opposite conduction type to the substrate 1 are formed respectively in the opening portion 13 and the polycrystal silicon film 11 to form a cell transistor comprising the series connection of a polycrystal silicon transistor with a MOS transistor. Thereby, since when holding data in the capacitor comprising a storing electrode 6, a capacitor insulation film 7 and a capacitor electrode 8 the drain region 11D is insulated from the semiconductor substrate 1, the data are prevented from leaking to the semiconductor substrate 1 to improve the data holding characteristic of the capacitor, lengthening its data holding time.

公开(公告)号：JPH0786510A

公开(公告)日：1995-03-31

申请号：JP18880293

申请日：1993-06-30

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H02H9/04 ,  H01L23/60

Abstract: PURPOSE:To improve resistance against electrostatic breakdown without increasing a chip area. CONSTITUTION:A common discharge line 1 is laid so as to pass through the neighbourhood of each of a Vcc terminal 10, an input terminal 11, a Vcc Q terminal 13, an output terminal 14, a GndQ terminal 15,..., a terminal In. The terminals excepting ground terminals 12, 16,... are connected with the common discharge line 1 through parallel elements such as voltage clamp elements 2-1-2-m and diodes 3-1-3-m.

公开(公告)号：JPH05128872A

公开(公告)日：1993-05-25

申请号：JP28581091

申请日：1991-10-31

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: G11C11/417 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE:To prevent destruction of a gate insulation film by providing a transistor, whose channel length is short, between the gate and the signal output terminal of an output transistor and thereby preventing a high voltage from generating between the gate and the source or the drain. CONSTITUTION:The channel length is set as mum, transistors(TRs) Q1, Q2 as 1.5, TRs Q3, Q4 as 1.0 which is sufficiently short, a control signal phi1, phi2 is inputted to the gates of TRs Q1, Q2, and an output signal is obtained for a signal output terminal Dout. TRs Q3, Q4 are not operated under a normal state, but an electrostatic discharge voltage in negative polarities is applied to the terminal Dout, the gate potential is dropped to the same potential as the terminal Dout. Therefore, a high voltage is not applied between the gate and the source of TR Q1 or between the gate and the drain of TR Q2; and since TRs Q3, Q4 are sufficiently short in the channel length, the charge is discharged before the gate is destroyed. Thus, the destruction of the gate insulation film is prevented.

公开(公告)号：JPH04348032A

公开(公告)日：1992-12-03

申请号：JP14953491

申请日：1991-05-24

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/312 ,  H01L21/318 ,  H01L21/768

Abstract: PURPOSE:To prevent any decrease in the thickness of a passivation film on the inner walls of a contact hole and improve the passivation performance. CONSTITUTION:An interlayer insulation film 105 is laid on a semiconductor substrate 101 having a diffusing layer 103 formed on the surface of the substrate 101, and a contact hole for exposing the surface of the diffusing layer 103 is made. Inner wall of the contact hole is covered, an Al wiring layer 106 contacting with the diffusing layer 103 is formed, and the first thin passivation film 107 is formed on the wiring layer. The contact hole is filled in with a polyimide layer 108 and the second passivation film 109 is formed thickly.

公开(公告)号：JPH03120835A

公开(公告)日：1991-05-23

申请号：JP26042289

申请日：1989-10-04

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/78

Abstract: PURPOSE:To obtain an LDD transistor of gate.drain.overlap structure wherein the controllability of low concentration diffusion width and gate.drain.overlap amount is superior and optimization is easy, by forming a side wall after a polycrystalline silicon film,which covers a gate electrode and is electrically connected with it, is formed. CONSTITUTION:A gate electrode 103 is formed on a silicon substrate 101 via a gate insulating film 102 ; a low concentration source.drain region 104a is formed by introducing impurity into the substrate 101 in a self-alignment manner to the gate electrode 103, a polycrystalline silicon film 105, which covers the gate electrode 103 and is electrically connected with it, is deposited; a silicon oxide film 106 is formed so as to cover the film 5, by anisotropically etching the film 106, it is left only on the side surface of the gate electrode 103, and a side wall is formed, the polycrystalline silicon film 105 is patterned in a self- alignment manner to the side wall by anisotropic etching, and left only on the side surface of the gate electrode 103 and under the side wall, thereby forming a high concentration source.drain region 107 in a self-alignment manner to the side wall.

公开(公告)号：JPS6412570A

公开(公告)日：1989-01-17

申请号：JP16923987

申请日：1987-07-06

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE:To prevent the generation of soft errors by a method wherein an opposite conductivity type deep semiconductor layer is provided in a semiconduc tor substrate and kept constant in potential, and charge is stored in a groove capacitor element with a pair of electrodes, one is the deep semiconductor layer and the other is a conductive layer buried in a groove. CONSTITUTION:Grooves 110a1 and 110b, an n-type deep semiconductor layer 108 containing at least the base of the grooves 110a1 and 110b, dielectric film 102a1 and 102b covering the surface of the grooves 110a1 and 110b, and conduc tor layers 103a1 and 103b through the intermediary of these films 102a1 and 102b are so provided in a p-type semiconductor substrate 101 as to extend from the primary surface to the inside. The side face of the groove 110b is inverted to be an n-type and layers 108 and 109 can be made to be conductive by applying a positive voltage onto the layer 103b, whereby the layer 108 can be kept constant in potential by fixing the layer 109 in potential. By these processes, charge can be stored at the film 103a1, which is controlled through a gate 104a1 and extracted outside. The layer 108 is kept constant in potential, so that a stored content hardly varies even if the substrate 101 absorbs alpha-rays.