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公开(公告)号：ES2179186T3
公开(公告)日：2003-01-16
申请号：ES96909524
申请日：1996-03-08
Applicant: QUALCOMM INC
Inventor： GILMORE ROBERT P
Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered utilizing a clean-up phase lock loop (PLL) to produce a spectrally pure reference signal and promote overall fast settling time. A second or primary phase lock loop, having a much faster settling time than the first PLL, adjusts the frequency of the reference signal generated by the clean-up PLL. In one embodiment, the DDS frequency synthesizer has a digital to analog (DAC) converter coupled to the clean-up PLL. Another embodiment uses a modified DDS (without a DAC or lookup table) and feeds the most significant bit (MSB) or overflow bit from the DAC accumulator into the "clean-up" PLL. In both embodiments, the resulting synthesizer has high spectral purity, fine frequency resolution and a fast settling time. Yet another embodiment uses a switching apparatus to bypass the "clean-up" PLL while it is settling on a new frequency. Once the "clean-up" PLL settles on the new frequency the switches are set to couple the "clean-up" PLL back into the synthesizer apparatus.
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公开(公告)号：PT815648E
公开(公告)日：2002-09-30
申请号：PT96909524
申请日：1996-03-08
Applicant: QUALCOMM INC
Inventor： GILMORE ROBERT P
Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered utilizing a clean-up phase lock loop (PLL) to produce a spectrally pure reference signal and promote overall fast settling time. A second or primary phase lock loop, having a much faster settling time than the first PLL, adjusts the frequency of the reference signal generated by the clean-up PLL. In one embodiment, the DDS frequency synthesizer has a digital to analog (DAC) converter coupled to the clean-up PLL. Another embodiment uses a modified DDS (without a DAC or lookup table) and feeds the most significant bit (MSB) or overflow bit from the DAC accumulator into the "clean-up" PLL. In both embodiments, the resulting synthesizer has high spectral purity, fine frequency resolution and a fast settling time. Yet another embodiment uses a switching apparatus to bypass the "clean-up" PLL while it is settling on a new frequency. Once the "clean-up" PLL settles on the new frequency the switches are set to couple the "clean-up" PLL back into the synthesizer apparatus.
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公开(公告)号：HK1010955A1
公开(公告)日：1999-07-02
申请号：HK98110019
申请日：1998-08-19
Applicant: QUALCOMM INC
Inventor： GILMORE ROBERT P , THOMPSON JAMES H
Abstract: A system and method for controlling the strength of a shared resource signal transmitted by the satellite transponder in a satellite communications system. The satellite communications system includes a gateway for transmitting communications signals including a shared resource signal, a satellite transponder for relaying the signals to at least one subscriber unit (for example, a phone), and at least one subscriber unit for receiving the signals. The method includes the steps of receiving the shared resource signal, at each subscriber unit, via the satellite transponder; measuring, at each subscriber unit, a signal strength for the received shared resource signal; sending the signal strengths to the gateway; and adjusting the power of the shared resource signal transmitted by the satellite transponder based on the signal strengths.
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34.发明专利
公开(公告)号：ZA9509997B
公开(公告)日：1997-08-25
申请号：ZA9509997
申请日：1995-11-23
Applicant: QUALCOMM INC
Inventor： GILMORE ROBERT P , LARAMIE DANIEL
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公开(公告)号：AR000494A1
公开(公告)日：1997-07-10
申请号：AR33443695
申请日：1995-11-29
Applicant: QUALCOMM INC
Inventor： GILMORE ROBERT P , LARAMIE DANIEL
Abstract: La invención se refiere a una disposición y un método para la utilización de una disposición sectorizada de antenas dentro de una estación celular debase, a efectos de proveer una cobertura redundante dentro de la célula rodeante. Una red de antenas de alimentación conecta los elementos de ladisposición sectorizada de antena, a un conjunto de transceptores de comunicación, incluyendo la red de alimentación, una disposición ordenada decombinadores para combinar haces de antenas seleccionadas al producirse el fallo de uno de los transceptores de comunicación. Una red de conmutación sirvepara proveer el haz combinado resultante, a uno de los transceptores de comunicación que es operativo. Como alternativa, ladisposición sectorizada deantena incluye un conjunto ordenado de antenas que tiene una pluralidad de elementos de antena conmutables, cada uno de ellos, conectado a uno de lostransceptores de comunicación. En otra variante, cada una de la antenas dentro de un conjunto ordenado primario, está dispuesta de modo de proyectar un hazsobre un sector simple, mientras que cada uno de los elementos dentro de un conjunto ordenado redundante, está disenado de modo de abarcar un par desectores adyacentes. El método para proveer una cobertura redundante incluye las etapas de proyectar haces sobre los sectores mediante una pluralidad deantenas, conectar éstas últimas a transceptores seleccionados y proveer el haz contenido a un transceptor operativo.
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Patent Agency Ranking
公开(公告)号：AU7243196A
公开(公告)日：1997-04-09
申请号：AU7243196
申请日：1996-09-23
Applicant: QUALCOMM INC
Inventor： KULBERG ERIC C , PANTON WILLIAM R , THOMPSON JAMES H , TIDWELL STEPHEN B , GILMORE ROBERT P
Abstract: A portable phone unit for use in satellite communication systems has a vertically correcting antenna module pivotally secured to the handset for free rotation about a pivot axis. The module contains a mechanism, such as a gravitational counterweight for urging the module to pivot into a predetermined vertical orientation regardless of the handset orientation. An antenna projects from the module in a direction which is vertically upright when the module is in its predetermined vertical orientation. A mast mounted antenna module can also be used to take advantage of dissimilar antenna segment weights for multiple frequency antennas. As the handset is moved into an angular orientation, the module pivots under the weight of the counterweight, or a portion of the antenna itself, until the antenna is oriented vertically.
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公开(公告)号：ES2095932T3
公开(公告)日：1997-03-01
申请号：ES91903171
申请日：1990-10-22
Applicant: QUALCOMM INC
Inventor： GILMORE ROBERT P
Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered and amplitude limited to reduce spurious noise. In one embodiment, the DDS frequency synthesizer is coupled to a phase lock loop which receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal. In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size. The synthesizer output frequency is a function of the input reference frequency, the number of bits in the digital word of the frequency control signal and the DDS step size as determined by the frequency control signal. Optional dividers may be provided in the feedback path which may further affect the synthesizer output frequency.
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38.发明专利
公开(公告)号：CA2206101A1
公开(公告)日：1996-06-06
申请号：CA2206101
申请日：1995-11-28
Applicant: QUALCOMM INC
Inventor： LARAMIE DANIEL , GILMORE ROBERT P
Abstract: A system and method for using a sectored antenna arrangement within a cellular base station to provide redundant coverage within the surrounding cell is disclosed herein. An antenna feed network connects elements of the sectored antenna arrangement to a set of communication transceivers (79, 80, 81), wherein the feed network includes a combiner array (92, 94, 96) for combining selected ones of the antenna beams upon failure of one of the communication transceivers (79, 80, 81). A switch network (102, 104, 106) serves to provide the resultant combined beam to an operative one of the communication transceivers. Alternately, the sectored antenna arrangement includes an antenna array having a plurality of switchable antenna elements A1-A3, each connected to one of the communication transceivers. The switchable antenna elements A1-A3 project a set of variable-width antenna beams over the plurality of cell sectors. Upon one of the communication transceivers becoming inoperative, an antenna control network operates to adjust beam width of a selected one of the variable-width antenna beams by switching configuration of an associated one of the switchable antenna elements (S1f, S2f, S3f, S1n, S2n, S3n). In another approach each antenna within a primary array (S1n, S2n, S3n) is disposed to project a beam over a single sector, while each element within a redundant array (S1f, S2f, S3f) is designed to encompass a pair of adjacent sectors. Upon one of the transceivers becoming inoperative, a transceiver nominally assigned to cover a sector neighboring the failed sector is connected to the element within the redundant array (S1f, S2f, S3f) encompassing both the failed and neighboring sectors.
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39.发明专利
公开(公告)号：AU7077391A
公开(公告)日：1991-10-21
申请号：AU7077391
申请日：1990-10-22
Applicant: QUALCOMM INC
Inventor： GILMORE ROBERT P
Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered and amplitude limited to reduce spurious noise. In one embodiment, the DDS frequency synthesizer is coupled to a phase lock loop which receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal. In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size. The synthesizer output frequency is a function of the input reference frequency, the number of bits in the digital word of the frequency control signal and the DDS step size as determined by the frequency control signal. Optional dividers may be provided in the feedback path which may further affect the synthesizer output frequency.
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40.发明专利
公开(公告)号：CA2079320A1
公开(公告)日：1991-09-30
申请号：CA2079320
申请日：1990-10-22
Applicant: QUALCOMM INC
Inventor： GILMORE ROBERT P
Abstract: A frequency synthesizer which uses a direct digital synthesizer (DDS) to generate a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. The DDS output signal is bandpass filtered and amplitude limited to reduce spurious noise. In one embodiment, the DDS frequency synthesizer is coupled to a phase lock loop which receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal. In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size. The synthesizer output frequency is a function of the input reference frequency, the number of bits in the digital word of the frequency control signal and the DDS step size as determined by the frequency control signal. Optional dividers may be provided in the feedback path which may further affect the synthesizer output frequency.
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