Abstract:
Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state for check node processing operations. The state for a check node is fully updated and then subject to an extraction process to generate check node to variable node messages. The signs of messages received from variable nodes may be stored by the check node processor module of the invention for use in message extraction. The check node processor can process messages in variable node order thereby allowing the variable node processor and check node processor to operate on messages in the same order reducing or eliminating the need to buffer and/or reorder messages passed between check nodes and variable nodes. Graph structures which allow check node processing on one graph iteration to proceed before the previous graph iteration has been completed are also described.
Abstract:
Methods and apparatus for scaling soft values (214) as part of an error correction decoding process are described. Accurate decoding depends on use of the appropriate scale factor. Selection and use of the scale factor to scale soft values is designed to improve and/or optimize decoder performance without the need for prior knowledge of the correct scale factor or the actual channel conditions at the time the signal from which the soft values were obtained was transmitted through a communications channel. The techniques of the present invention assumes that the soft values to be processed were transmitted through a communications channel having a quality that can be accurately described by a channel quality value (200). A scale factor is determined from the distribution of soft value (208) to be scaled (212) and an assumption that the channel through which they were transmitted was of the quality corresponding to a pre-selected channel quality value (210).