公开(公告)号：WO2016014213A1

公开(公告)日：2016-01-28

申请号：PCT/US2015/038013

申请日：2015-06-26

Applicant: QUALCOMM INCORPORATED

Inventor： CODRESCU, Lucian ,  MAHURIN, Eric, Wayne

IPC: G06F9/30

CPC classification number: G06F15/82 ,  G06F9/3001 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/3012

Abstract: Parallelization of scalar operations by vector processors using data-indexed accumulators in vector register files, related circuits, methods, and computer-readable media are disclosed. In one aspect, a vector processor comprises a vector register file providing a plurality of write ports and a plurality of vector registers each providing a plurality of accumulators. The vector processor receives an input data vector. For each of the plurality of write ports, the vector processor executes vector operation(s) for accessing an input data value of the input data vector, and determining, based on the input data value, a register index for a vector register among the plurality of vector registers, and an accumulator index for an accumulator among the plurality of accumulators of the vector register. Based on the register index, a register value is retrieved from the register index, and a scalar operation is performed based on the register value and the accumulator index.

Abstract translation: 公开了使用向量寄存器文件，相关电路，方法和计算机可读介质中的数据索引累加器的矢量处理器的标量运算的并行化。 一方面，向量处理器包括提供多个写入端口的向量寄存器文件和多个向量寄存器，每个向量寄存器提供多个累加器。 向量处理器接收输入数据向量。 对于多个写入端口中的每一个，向量处理器执行用于访问输入数据向量的输入数据值的向量操作，并且基于输入数据值，确定多个写入端口中的向量寄存器的寄存器索引 矢量寄存器的多个累加器中的累加器的累加器索引。 基于寄存器索引，从寄存器索引检索寄存器值，并且基于寄存器值和累加器索引执行标量运算。

公开(公告)号：WO2013109648A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021774

申请日：2013-01-16

Applicant: QUALCOMM INCORPORATED

Inventor： SASSONE, Peter G. ,  KOOB, Christopher Edward ,  VANTREASE, Dana M. ,  VENKUMAHANTI, Suresh K. ,  CODRESCU, Lucian

IPC: G06F12/08 ,  G06F1/32

CPC classification number: G06F12/0804 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0806 ,  G06F12/0846 ,  G06F2212/1028 ,  G06F2212/502 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Embodiments disclosed in the detailed description include hybrid writethrough/ write-back cache policy managers, and related systems and methods. A cache write policy manager is configured to determine whether at least two caches among a plurality of parallel caches are active. If all of one or more other caches are not active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-back cache policy. In this manner, the cache write policy manager may conserve power and/or increase performance of a singly active processor core. If any of the one or more other caches are active, the cache write policy manager is configured to instruct an active cache among the parallel caches to apply a write-through cache policy. In this manner, the cache write policy manager facilitates data coherency among the parallel caches when multiple processor cores are active.

Abstract translation: 在详细描述中公开的实施例包括混合写入/回写高速缓存策略管理器以及相关的系统和方法。 高速缓存写策略管理器被配置为确定多个并行高速缓存中的至少两个高速缓存是否是活动的。 如果所有一个或多个其他高速缓存不活动，则缓存写策略管理器被配置为指示并行高速缓存之间的活动高速缓存来应用回写高速缓存策略。 以这种方式，缓存写入策略管理器可以节省单个活动处理器核心的功率和/或提高性能。 如果一个或多个其他高速缓存中的任一个是活动的，则高速缓存写策略管理器被配置为指示并行高速缓存中的活动高速缓存来应用直写高速缓存策略。 以这种方式，当多个处理器核心处于活动状态时，缓存写入策略管理器便于并行高速缓存之间的数据一致性。

公开(公告)号：WO2013052684A2

公开(公告)日：2013-04-11

申请号：PCT/US2012/058780

申请日：2012-10-04

Applicant: QUALCOMM INCORPORATED

Inventor： VENKUMAHANTI, Suresh K. ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  CHEN, Xufeng ,  ZHONG, Peixin

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt.

Abstract translation: 用于减少多线程处理器中的中断等待时间的系统和方法

第一中断控制器耦合到多线程处理器。 第二中断控制器被配置为将第一中断和第一向量标识符传送到第一中断控制器，其中第一中断控制器被配置为处理第一中断和第一向量标识符，并将处理后的中断发送到多线程中的线程 螺纹处理器。 逻辑配置为确定多线程处理器何时准备好接收第二个中断。 专用线用于向第二中断控制器传达指示多线程处理器准备好接收第二中断的指示。

公开(公告)号：WO2013025641A1

公开(公告)日：2013-02-21

申请号：PCT/US2012/050648

申请日：2012-08-13

Applicant: QUALCOMM INCORPORATED ,  ZENG, Mao ,  CODRESCU, Lucian ,  PLONDKE, Erich James

Inventor： ZENG, Mao ,  CODRESCU, Lucian ,  PLONDKE, Erich James

IPC: G06F9/30

CPC classification number: G06F9/30018 ,  G06F9/30032

Abstract: An instruction specifies a source value and an offset value. Upon execution of the instruction, a first result of the instruction and a second result of the instruction are generated. The first result is a first portion of the source value and the second result is a second portion of the source value.

Abstract translation: 指令指定源值和偏移值。 在执行指令时，生成指令的第一结果和指令的第二结果。 第一个结果是源值的第一部分，第二个结果是源值的第二部分。

公开(公告)号：WO2013013100A1

公开(公告)日：2013-01-24

申请号：PCT/US2012/047488

申请日：2012-07-19

Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich, James ,  CODRESCU, Lucian ,  TABONY, Charles, Joseph ,  INGLE, Ajay, Anant ,  VENKUMAHANTI, Suresh, K. ,  MENEZES, Evandro, Carlos

Inventor： PLONDKE, Erich, James ,  CODRESCU, Lucian ,  TABONY, Charles, Joseph ,  INGLE, Ajay, Anant ,  VENKUMAHANTI, Suresh, K. ,  MENEZES, Evandro, Carlos

IPC: G06F9/30

CPC classification number: G06F9/30054 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/322 ,  G06F9/327

Abstract: An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.

Abstract translation: 一种装置包括存储包含操作码和操作数的指令的存储器。 操作数指定存储立即值的寄存器的立即值或寄存器指示符。 立即值可用于标识函数调用地址。 功能调用地址可以从多个功能调用地址中选择。

公开(公告)号：WO2011063362A1

公开(公告)日：2011-05-26

申请号：PCT/US2010/057685

申请日：2010-11-22

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich, James ,  CODRESCU, Lucian ,  INGLE, Ajay, Anant ,  ZENG, Mao ,  KOOB, Christopher, Edward ,  TABONY, Charles, Joseph

Inventor： PLONDKE, Erich, James ,  CODRESCU, Lucian ,  INGLE, Ajay, Anant ,  ZENG, Mao ,  KOOB, Christopher, Edward ,  TABONY, Charles, Joseph

IPC: G06F9/30 ,  H04N7/26 ,  H03M7/40

CPC classification number: H03M7/4006 ,  G06F9/30018 ,  G06F9/3895 ,  H04N19/13 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61

Abstract: A dedicated arithmetic decoding instruction is disclosed. In a particular embodiment, an apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute general purpose instructions and to execute a dedicated arithmetic decoding instruction retrieved from the memory.

Abstract translation: 公开了专用算术解码指令。 在特定实施例中，装置包括存储器和耦合到存储器的处理器。 处理器被配置为执行通用指令并且执行从存储器检索的专用算术解码指令。

公开(公告)号：WO2010102048A1

公开(公告)日：2010-09-10

申请号：PCT/US2010/026106

申请日：2010-03-03

Applicant: QUALCOMM INCORPORATED ,  KOOB, Christopher, Edward ,  INGLE, Ajay, Anant ,  CODRESCU, Lucian ,  SHEN, Jian

Inventor： KOOB, Christopher, Edward ,  INGLE, Ajay, Anant ,  CODRESCU, Lucian ,  SHEN, Jian

IPC: G06F12/08 ,  G06F17/50

CPC classification number: G06F12/0895 ,  G06F12/0802 ,  G06F12/0864 ,  G06F17/505 ,  G06F2212/2515 ,  G06F2212/601

Abstract: In a particular embodiment, a cache is disclosed that includes a tag state array that includes a tag area addressable by a set index. The tag state array also includes a state area addressable by a state address, where the set index and the state address include at least one common bit.

Abstract translation: 在特定实施例中，公开了一种包括标签状态阵列的高速缓存，其包括可由设定索引寻址的标签区域。 标签状态阵列还包括可由状态地址寻址的状态区域，其中设置索引和状态地址包括至少一个公共位。

公开(公告)号：WO2010039457A1

公开(公告)日：2010-04-08

申请号：PCT/US2009/057453

申请日：2009-09-18

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  GURSKI, Remi ,  KRITHIVASAN, Shankar

Inventor： PLONDKE, Erich ,  CODRESCU, Lucian ,  GURSKI, Remi ,  KRITHIVASAN, Shankar

IPC: G06F9/305 ,  G06F9/38

CPC classification number: G06F9/30018 ,  G06F7/584 ,  G06F9/30003 ,  G06F9/30032

Abstract: A system and method to execute a linear feedback-shift instruction is disclosed. In a particular embodiment the method includes executing an instruction at a processor by receiving source data and executing a bitwise logical operation on the source data and on reference data to generate intermediate data. The method further includes determining a parity value of the intermediate data, shifting the source data, and entering the parity value of the intermediate data into a data field of the shifted source data to produce resultant data.

Abstract translation: 公开了一种执行线性反馈移位指令的系统和方法。 在特定实施例中，该方法包括通过接收源数据并对源数据和参考数据执行逐位逻辑运算来执行处理器处的指令以产生中间数据。 该方法还包括确定中间数据的奇偶校验值，移位源数据，并将中间数据的奇偶校验值输入到移位的源数据的数据字段中，以产生结果数据。

公开(公告)号：WO2010033569A1

公开(公告)日：2010-03-25

申请号：PCT/US2009/057123

申请日：2009-09-16

Applicant: QUALCOMM Incorporated ,  PLONDKE, Erich James ,  CODRESCU, Lucian

Inventor： PLONDKE, Erich James ,  CODRESCU, Lucian

IPC: G06F9/48

CPC classification number: G06F9/4818

Abstract: A multithreaded processor capable of allocating interrupts is described. In one embodiment, the multithreaded processor includes an interrupt module and threads for executing tasks. The interrupt module can identify a priority for each thread based on a task priority for tasks being executed by the threads and assign an interrupt to a thread based at least on its priority.

Abstract translation: 描述了能够分配中断的多线程处理器。 在一个实施例中，多线程处理器包括用于执行任务的中断模块和线程。 中断模块可以基于线程执行的任务的任务优先级来识别每个线程的优先级，并且至少基于其优先级为线程分配中断。

公开(公告)号：WO2009111198A1

公开(公告)日：2009-09-11

申请号：PCT/US2009/034839

申请日：2009-02-23

Applicant: QUALCOMM INCORPORATED ,  INGLE, Ajay A. ,  PLONDKE, Erich J. ,  CODRESCU, Lucian

Inventor： INGLE, Ajay A. ,  PLONDKE, Erich J. ,  CODRESCU, Lucian

IPC: G06F9/38

CPC classification number: G06F9/383 ,  G06F9/3001

Abstract: A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The adder is further configures for the first instruction to determine a value from an arithmetic operation if the first instruction is an arithmetic operation instruction.

Abstract translation: 描述了包括双功能加法器的系统。 在一个实施例中，该系统包括加法器。 如果第一指令是硬件预取指令，则加法器被配置用于第一指令以确定用于硬件预取的地址。 如果第一指令是算术运算指令，则加法器进一步配置用于从算术运算确定值的第一指令。