公开(公告)号：WO2013163473A1

公开(公告)日：2013-10-31

申请号：PCT/US2013/038286

申请日：2013-04-25

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Bo ,  DOROSENCO, Alexander

IPC: H03C3/09 ,  H03C5/00

CPC classification number: H03C3/02 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03C5/00 ,  H04L27/2003 ,  H04L27/2032

Abstract: An ultra-wide band frequency modulator is disclosed. The frequency modulator includes a direct modulation phase lock loop that receives a small component. The frequency modulator also includes a delay module that produces a plurality of delay lines. The frequency modulator further includes an edge selector that receives a large component and the plurality of delay lines.

Abstract translation: 公开了一种超宽带频率调制器。 频率调制器包括接收小分量的直接调制锁相环。 频率调制器还包括产生多个延迟线的延迟模块。 频率调制器还包括边缘选择器，其接收大的分量和多个延迟线。

公开(公告)号：WO2009134884A1

公开(公告)日：2009-11-05

申请号：PCT/US2009/042109

申请日：2009-04-29

Applicant: QUALCOMM INCORPORATED ,  SUN, Bo ,  ANIRUDDHAN, Sankaran ,  SRIDHARA, Sriramgopal

Inventor： SUN, Bo ,  ANIRUDDHAN, Sankaran ,  SRIDHARA, Sriramgopal

IPC: G06F1/12 ,  G06F1/32

CPC classification number: G06F1/12 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

Abstract: A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other.

Abstract translation: 一种用于同步一个或多个除法器单元的相位的装置的方法包括在主分频器单元上供电以提供参考信号。 从分频器单元的相位通过在从分频器单元处提供通电脉冲而与来自主分频器单元的参考信号同步，使用数字控制的振荡器将从分频器单元的相位与参考信号同步， 在通电脉冲的上升沿之后的第一预定延迟时段之后的从分频器单元上。 通过将从属分频器单元与来自主分频器单元的参考信号同步，任何数量的从分频器单元可以通电并且彼此同相。

公开(公告)号：WO2009086021A1

公开(公告)日：2009-07-09

申请号：PCT/US2008/087548

申请日：2008-12-18

Applicant: QUALCOMM INCORPORATED ,  MALDONADO, David ,  SEE, Puay, Hoe ,  SUN, Bo ,  ZHANG, Guang ,  WALKER, Brett, C.

Inventor： MALDONADO, David ,  SEE, Puay, Hoe ,  SUN, Bo ,  ZHANG, Guang ,  WALKER, Brett, C.

IPC: H04B1/04 ,  H04B1/40

CPC classification number: H04B1/0483 ,  H04B1/40 ,  H04B2001/0416

Abstract: A method for controlling the voltage of signals used to control power amplifiers is described. A first multiplexer and a second multiplexer are set to an enabling signal. The first multiplexer is on a first integrated circuit and the second multiplexer is on a second integrated circuit. A command is written to the first multiplexer to set the first multiplexer to one of a plurality of control signals used to control a power amplifier. A command is written to the second multiplexer to select one of the plurality of control signals that maps to the first multiplexer. The second integrated circuit is connected to a power supply.

Abstract translation: 描述了用于控制用于控制功率放大器的信号的电压的方法。 第一多路复用器和第二多路复用器被设置为使能信号。 第一多路复用器在第一集成电路上，第二多路复用器在第二集成电路上。 一个命令被写入到第一多路复用器中，以将第一多路复用器设置成用于控制功率放大器的多个控制信号之一。 一个命令被写入第二多路复用器以选择映射到第一多路复用器的多个控制信号之一。 第二集成电路连接到电源。

公开(公告)号：WO2009079468A3

公开(公告)日：2009-06-25

申请号：PCT/US2008/086856

申请日：2008-12-15

Applicant: QUALCOMM Incorporated ,  SUN, Bo ,  ANIRUDDHAN, Sankaran

Inventor： SUN, Bo ,  ANIRUDDHAN, Sankaran

IPC: H03F1/02 ,  H03F3/19 ,  H03F3/24 ,  H03F3/30 ,  H03F1/32 ,  H03G3/20 ,  H03G3/30 ,  H03F1/30

Abstract: Techniques are provided for dynamically biasing an amplifier to extend the amplifier's operating range while conserving power. In an embodiment, a detector (310) is provided to measure the amplifier output to determine an operating region of the amplifier. The output of the detector (310) may be input to a bias adjuster (320), which outputs a dynamic voltage level supplied to at least one bias transistor (M81) in the amplifier. Multiple embodiments of the detector and bias adjuster are disclosed.

公开(公告)号：WO2009036397A1

公开(公告)日：2009-03-19

申请号：PCT/US2008/076321

申请日：2008-09-12

Applicant: QUALCOMM INCORPORATED ,  ANIRUDDHAN, Sankaran ,  SUN, Bo ,  JAYARAMAN, Arun ,  SAHOTA, Gurkanwal, Singh

Inventor： ANIRUDDHAN, Sankaran ,  SUN, Bo ,  JAYARAMAN, Arun ,  SAHOTA, Gurkanwal, Singh

IPC: H03D7/16 ,  H04B1/04

CPC classification number: H03D7/165 ,  H04B1/0483 ,  H04B2001/0416 ,  H04B2001/0491

Abstract: A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.

Abstract translation: 电路接收第一信号（例如，基带信号）并将其与本地振荡器（LO）信号混合，并输出第二信号（例如，RFOUT信号）。 该电路包括多个相同的混频器和分频器对（MFDP）电路。 每个MFDP可以单独启用。 每个MFDP包括混频器和分频器，为混频器提供本地版本的LO信号。 MFDP输出耦合在一起，使得第二信号（RFOUT）的输出功率是各种MFDP的组合输出功率。 通过控制使能的MFDP的数量，控制第二信号的输出功率。 由于MFDP都具有相同的布局，因此输出功率步长的精度提高。 由于电路内的LO信号功率与启用MFDP的数量成比例地自动变化，因此避免了本地振荡器泄漏问题。

公开(公告)号：EP2289170A2

公开(公告)日：2011-03-02

申请号：EP09763396.0

申请日：2009-06-08

Applicant: QUALCOMM Incorporated

Inventor： SUN, Bo ,  BALLANTYNE, Gary John ,  RANGARAJAN, Rajagopalan

IPC: H03L7/099 ,  H04B1/04 ,  H04B1/16 ,  H03B5/12

CPC classification number: H03L7/099 ,  H03L2207/06

Abstract: Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed.

公开(公告)号：EP2269312A1

公开(公告)日：2011-01-05

申请号：EP09717130.0

申请日：2009-03-03

Applicant: QUALCOMM Incorporated

Inventor： SUN, Bo ,  YANG, Zixiang

IPC: H03M1/20 ,  H03M1/50

CPC classification number: G04F10/005

Abstract: A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.

公开(公告)号：EP2250732A1

公开(公告)日：2010-11-17

申请号：EP09716634.2

申请日：2009-03-03

Applicant: QUALCOMM Incorporated

Inventor： SUN, Bo ,  YANG, Zixiang

IPC: H03M1/50

CPC classification number: G04F10/005

Abstract: Techniques for enabling a time-to-digital converter (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.

公开(公告)号：EP2203978A2

公开(公告)日：2010-07-07

申请号：EP08843278.6

申请日：2008-10-23

Applicant: QUALCOMM Incorporated

Inventor： SUN, Bo ,  SAHOTA, Gurkanwal Singh ,  WU, Yue

IPC: H03L7/10 ,  H03L7/107 ,  H03L7/093 ,  H03L7/08

CPC classification number: H03L7/197 ,  H03J7/065 ,  H03L1/00 ,  H03L7/0802 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107 ,  H03L2207/06

Abstract: A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.

公开(公告)号：EP2156561A1

公开(公告)日：2010-02-24

申请号：EP08770948.1

申请日：2008-06-13

Applicant: QUALCOMM Incorporated

Inventor： SEO, Dongwon ,  SUN, Bo ,  SAHOTA, Gurkanwal Singh (Kamal) ,  MISHRA, Manu

IPC: H03M1/00

CPC classification number: H03M1/002 ,  H03M1/682 ,  H03M1/747

Abstract: A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values.