公开(公告)号：WO2014159255A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/022711

申请日：2014-03-10

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Bo

IPC: G01R19/165 ,  G01R15/08 ,  G01R15/04 ,  G05F1/46 ,  G01R15/09

CPC classification number: G05F3/08 ,  G01R15/04 ,  G01R15/08 ,  G01R15/09 ,  G01R19/16519 ,  G01R19/16552 ,  G05F1/465

Abstract: A voltage divider circuit (103) is provided that automatically and dynamically adjusts its voltage divider chains as a supply voltage changes. The voltage divider circuit includes a plurality of voltage divider branches (102, 104, 106) having different divider factors to divide the supply voltage (VDD) and obtain a divided supply voltage (Vm_A, Vm_B, Vm_i). Additionally, a control circuit (112) is coupled to the plurality of voltage divider branches and adapted to automatically monitor the supply voltage and dynamically select (116) a voltage divider branch from among the plurality of voltage divider branches to maintain a selected divided supply voltage within a pre-determined voltage range.

Abstract translation: 提供分压器电路（103），其随着电源电压的变化自动且动态地调节其分压器链。 分压器电路包括具有不同分频器因数的多个分压器分支（102,104,106），以分割电源电压（VDD）并获得分压电源电压（Vm_A，Vm_B，Vm_i）。 另外，控制电路（112）耦合到多个分压器分支并且适于自动监测电源电压并且动态地选择（116）多个分压器分支中的分压器分支以保持所选择的分开的电源电压 在预定的电压范围内。

公开(公告)号：WO2014150707A2

公开(公告)日：2014-09-25

申请号：PCT/US2014/024035

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： TANG, Yi ,  SUN, Bo

CPC classification number: H03M1/50 ,  G04F10/005 ,  H03L7/08 ,  H03L7/0991 ,  H03L2207/50

Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.

Abstract translation: 时间 - 数字转换器将参考时钟信号和振荡信号的转换时间之间的差异转换成数值信号，其数值信号与转换时序差成比例。 该时间 - 数字转换器包括边缘检测器，时间 - 电压转换器和模 - 数转换器。 边缘检测器适于在参考时钟信号的每个周期期间检测最靠近参考时钟信号的边缘的振荡信号的边沿（跃迁）。 时间 - 电压转换器适于产生与所检测的振荡信号的边沿与基准时钟信号的边沿之间的时间差成比例的模拟信号。 模拟 - 数字转换器适于将模拟信号转换成数字信号，该数字信号的值与振荡信号的检测到的边沿的出现与参考时钟信号的边沿之间的差成比例。

公开(公告)号：WO2011072248A1

公开(公告)日：2011-06-16

申请号：PCT/US2010/059936

申请日：2010-12-10

Applicant: QUALCOMM INCORPORATED ,  SUN, Bo

Inventor： SUN, Bo

IPC: G05F1/46 ,  H03M1/80 ,  H03G3/30

CPC classification number: G05F1/46 ,  H03F1/0261 ,  H03F1/223 ,  H03F3/195 ,  H03F2200/108 ,  H03F2200/27 ,  H03F2200/294 ,  H03F2200/321 ,  H04B2001/6908

Abstract: An apparatus for generating a bias voltage for an active device is disclosed, comprising a first voltage source, a capacitive element adapted to generate a charge in response to the first voltage source, and a first switching element adapted to deliver the charge to generate the bias voltage for the active device. The apparatus may comprise a controller adapted to control a capacitive element based on one or more characteristics of the active device. Alternatively, the controller may also control the capacitance of the capacitive element based on a reference voltage that is, in turn, based on one or more characteristics of the active device. The apparatus may also comprise a second voltage source adapted to generate a second voltage from which the bias voltage may be generated. The second voltage may be based on one or more characteristics of the active device. The apparatus may comprise a second switching element adapted to selectively enable and disable the active device.

Abstract translation: 公开了一种用于产生用于有源器件的偏置电压的装置，包括：第一电压源，适于响应于第一电压源产生电荷的电容元件;以及适于传送电荷以产生偏置的第一开关元件 有源器件的电压。 该装置可以包括适于基于有源装置的一个或多个特性来控制电容元件的控制器。 或者，控制器还可以基于参考电压来控制电容元件的电容，参考电压又是基于有源器件的一个或多个特性。 该装置还可以包括适于产生可产生偏置电压的第二电压的第二电压源。 第二电压可以基于有源器件的一个或多个特性。 该装置可以包括适于选择性地启用和禁用有源装置的第二开关元件。

公开(公告)号：WO2004068700A9

公开(公告)日：2004-08-12

申请号：PCT/US2004/001642

申请日：2004-01-21

Applicant: QUALCOMM INCORPORATED ,  SUN, Bo

Inventor： SUN, Bo

IPC: H03F3/68

Abstract: A feedforward nonlinearity cancellation scheme is used to improve the linearity of a low noise amplifier (LNA). An LNA incorporates a main amplifier and an auxiliary amplifier couple to receive the same input. The outputs of the main amplifier and the auxiliary amplifier are also coupled. The auxiliary amplifier may be implemented as a very low power auxiliary amplifier having a very low linearity. The output of the auxiliary amplifier contains third-order intermodulation (IM3) products that are of similar amplitude, but opposite phase, to the IM3 products generated by the main amplifier. With the outputs of the main amplifier and the auxiliary amplifier coupled, their respective IM3 products are summed together and effectively cancel each other out. As a result, the output of the LNA contains substantially no IM3 products, and the linearity of the LNA is substantially improved.

公开(公告)号：WO2009132147A1

公开(公告)日：2009-10-29

申请号：PCT/US2009/041461

申请日：2009-04-22

Applicant: QUALCOMM INCORPORATED ,  SUN, Bo ,  YANG, Zixiang ,  SAHOTA, Gurkanwal, Singh

Inventor： SUN, Bo ,  YANG, Zixiang ,  SAHOTA, Gurkanwal, Singh

IPC: H03L7/085

CPC classification number: H03L7/085 ,  H03L7/18 ,  H03L2207/50

Abstract: A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.

Abstract translation: 公开了一种系统和方法，用于校准数字锁相环（DPLL）的时间 - 数字转换器（TDC）的上电门控窗口。 门控窗口被校准，以确保DPLL的正常运行，同时以高效的方式操作TDC。 特别地，该技术需要将TDC门控窗口的宽度设置为默认值; 操作DPLL直到控制回路基本锁定; 同时监视由DPLL的相位误差装置产生的相位误差信号，将TDC门控窗口的宽度减小预定量; 在相位误差到达或超过预定阈值的时间基本上确定TDC门控窗口的当前宽度; 并且将TDC门控窗口的当前宽度增加预定量以构成TDC门控窗口的操作宽度的误差范围。

公开(公告)号：WO2009111496A1

公开(公告)日：2009-09-11

申请号：PCT/US2009/035913

申请日：2009-03-03

Applicant: QUALCOMM INCORPORATED ,  SUN, Bo ,  YANG, Zixiang

Inventor： SUN, Bo ,  YANG, Zixiang

IPC: H03M1/20 ,  H03M1/50

CPC classification number: G04F10/005

Abstract: A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.

Abstract translation: 时间 - 数字转换器（TDC）可以具有比逆变器的传播延迟更精细的分辨率。 在一个示例中，分数延迟元件电路接收TDC输入信号并由此产生作为第一信号的时移传真的第二信号。 第一信号被提供给第一延迟线时间戳电路（DLTC），第二信号被提供给第二DLTC。 第一DLTC产生指示参考输入信号与TDC的边缘和第一信号的边缘之间的时间的第一时间戳。 第二DLTC产生指示参考输入信号的边缘与第二信号的边缘之间的时间的第二时间戳。 组合第一和第二时间戳并且一起构成具有比第一或第二时间戳更精细的分辨率的高分辨率整体TDC时间戳。

公开(公告)号：WO2009055622A3

公开(公告)日：2009-04-30

申请号：PCT/US2008/081033

申请日：2008-10-23

Applicant: QUALCOMM Incorporated ,  SUN, Bo ,  SAHOTA, Gurkanwal Singh ,  WU, Yue

Inventor： SUN, Bo ,  SAHOTA, Gurkanwal Singh ,  WU, Yue

IPC: H03L7/10 ,  H03L7/107 ,  H03L7/093 ,  H03L7/08

Abstract: A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.

公开(公告)号：WO2008067256A1

公开(公告)日：2008-06-05

申请号：PCT/US2007/085541

申请日：2007-11-26

Applicant: QUALCOMM INCORPORATED ,  SUN, Bo ,  JAYARAMAN, Arun ,  BALLANTYNE, Gary J. ,  SAHOTA, Gurkanwal S.

Inventor： SUN, Bo ,  JAYARAMAN, Arun ,  BALLANTYNE, Gary J. ,  SAHOTA, Gurkanwal S.

IPC: H03L7/00

CPC classification number: H03L7/10 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H03L7/099

Abstract: This disclosure describes designs for a digitally controlled oscillator (DCO). The DCO can overcome many of the shortcomings associated with conventional voltage controlled oscillators (VCOs), and may improve wireless communication devices. The described DCO may improve the frequency synthesis process, reduce noise in a wireless communication device, and allow for simplification of various components of the device.

Abstract translation: 本公开描述了数字控制振荡器（DCO）的设计。 DCO可以克服与常规压控振荡器（VCO）相关的许多缺点，并且可以改进无线通信设备。 所描述的DCO可以改善频率合成过程，减少无线通信设备中的噪声，并且允许简化设备的各种组件。

公开(公告)号：WO2019203968A1

公开(公告)日：2019-10-24

申请号：PCT/US2019/022675

申请日：2019-03-18

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Bo ,  TANG, Yi ,  BUTTERFIELD, Daniel

IPC: H03K3/011 ,  H03K5/131

Abstract: Aspects generally relate to reducing delay, or phase jitter, in high speed signals transmission. Variations in power supply to ground potential changes the amount of delay introduced by transmit circuity into the signal being transmitted, resulting in jitter, or phase noise, in the transmitted signal. To reduce phase jitter, or phase noise, aspects disclosed include a variable impedance circuit coupled to the signal distribution network, the impedance level of the variable impedance circuit is adjusted in response to variation in the supply to ground potential, such that the delay introduced by the impedance compensates for changes in the delay due to variations in supply to ground potential, resulting in substantially constant delay.

公开(公告)号：WO2015006192A1

公开(公告)日：2015-01-15

申请号：PCT/US2014/045539

申请日：2014-07-07

Applicant: QUALCOMM INCORPORATED

Inventor： BALLANTYNE, Gary, John ,  SUN, Bo ,  TANG, Yi ,  YANG, Zixiang ,  ENSAFDARAN, Masoud

IPC: H03L7/099

CPC classification number: H03L7/0991 ,  H03B5/1265 ,  H03B2200/0088 ,  H03B2201/025 ,  H03B2202/017 ,  H03J5/24 ,  H03J2200/10 ,  H03J2200/36 ,  H03L7/099 ,  H03L2207/50

Abstract: One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.

Abstract translation: 一个特征涉及包含可变电容器和降噪电路的数字控制振荡器（DCO）。 可变电容器具有控制DCO的输出频率的可变电容值。 可变电容值基于由第一电容器组提供的第一组电容值，由第二电容器组提供的第二组电容值和由辅助电容器组提供的辅助组电容值。 噪声降低电路适于通过调整辅助电容电容值来调节可变电容值，同时保持第一组电容值和/或第二组电容值中的至少一个基本上不变。 在调整可变电容值之前，噪声降低电路可以确定接收的输入DCO控制字在电容器组敏感边界之间跳变。