SOI-BASED PHOTONIC BANDGAP DEVICES
    32.
    发明申请
    SOI-BASED PHOTONIC BANDGAP DEVICES 审中-公开
    基于SOI的光电带宽器件

    公开(公告)号:WO2005079258A3

    公开(公告)日:2006-06-01

    申请号:PCT/US2005004123

    申请日:2005-02-09

    CPC classification number: G02F1/025 G02F2202/32

    Abstract: An SOI-based photonic bandgap (PBG) electro-optic device utilizes a patterned PBG structure to define a two-dimensional waveguide within an active waveguiding region of the SOI electro-optic device. The inclusion of the PBG columnar arrays within the SOI structure results in providing extremely tight lateral confinement of the optical mode within the waveguiding structure, thus significantly reducing the optical loss. By virtue of including the PBG structure, the associated electrical contacts may be placed in closer proximity to the active region without affecting the optical performance, thus increasing the switching speed of the electro-optic device. The overall device size, capacitance and resistance also reduced as a consequence of using PBGs for lateral mode confinement.

    Abstract translation: 基于SOI的光子带隙(PBG)电光器件利用图案化的PBG结构来在SOI电光器件的有源波导区域内限定二维波导。 在SOI结构中包含PBG柱状阵列导致在波导结构内提供光学模式的非常紧密的侧向约束,从而显着减少光学损耗。 通过包括PBG结构,相关联的电触点可以放置在更接近有源区域而不影响光学性能,从而增加电光器件的切换速度。 由于使用PBG用于横向模式限制,整个设备尺寸,电容和电阻也减小了。

    SILICON NANOTAPER COUPLERS AND MODE-MATCHING DEVICES
    33.
    发明申请
    SILICON NANOTAPER COUPLERS AND MODE-MATCHING DEVICES 审中-公开
    硅纳米粒子耦合器和模式匹配器件

    公开(公告)号:WO2005077110A2

    公开(公告)日:2005-08-25

    申请号:PCT/US2005004507

    申请日:2005-02-10

    CPC classification number: G02B6/1228 G02B6/4204

    Abstract: An arrangement for providing optical coupling between a free-space propagating optical signal and an ultrathin silicon waveguide formed in an upper silicon layer of a silicon-on-insulator (SOI) structure includes a silicon nanotaper structure formed in the upper silicon layer (SOI layer) of the SOI structure and coupled to the ultrathin silicon waveguide. A dielectric waveguide coupling layer, with a refractive index greater than the index of the dielectric insulating layer but less than the refractive index of silicon, is disposed so as to overly a portion of the dielectric insulating layer in a region where an associated portion of the SOI layer has been removed. An end portion of the dielectric waveguide coupling layer is disposed to overlap an end section of the silicon nanotaper to form a mode conversion region between the free-space propagating optical signal and the ultrathin silicon waveguide. A free-space optical coupling arrangement (such as a prism or grating) is disposed over the dielectric waveguide coupling layer and used to couple a propagating optical signal between free space and the dielectric waveguide coupling layer and thereafter into the ultrathin silicon waveguide.

    Abstract translation: 用于在自由空间传播的光信号和形成在绝缘体上硅(SOI))结构的上硅层中的超薄硅波导之间提供光耦合的装置包括形成在上硅层(SOI层)中的硅纳米锥结构 )和耦合到超薄硅波导。 具有大于介电绝缘层的折射率但小于硅的折射率的折射率的介质波导耦合层被布置成过度地在介电绝缘层的一部分中的相关部分 SOI层已被去除。 电介质波导耦合层的端部设置成与硅纳米锥的端部部分重叠以在自由空间传播的光信号和超薄硅波导之间形成模式转换区域。 自由空间光耦合装置(诸如棱镜或光栅)设置在介质波导耦合层之上,用于将传播的光信号耦合在自由空间与介质波导耦合层之间,然后耦合到超薄硅波导中。

    HIGH-SPEED SILICON-BASED ELECTRO-OPTIC MODULATOR
    34.
    发明申请
    HIGH-SPEED SILICON-BASED ELECTRO-OPTIC MODULATOR 审中-公开
    高速硅基电光调制器

    公开(公告)号:WO2004088394A3

    公开(公告)日:2005-03-31

    申请号:PCT/US2004008814

    申请日:2004-03-23

    Applicant: SIOPTICAL INC

    Abstract: A silicon-based electro-optic modulator (30) is based on forming a gate region of a first conductivity to partially overly a body region of a second conductivity type, with a relatively thin dielectric layer (10) interposed between the contiguous portions of the gate and body regions (12, 10). The modulator may be formed on an SOI platform, with the body region formed in the relatively thin silicon surface layer of the SOI structure and the gate region formed of a relatively thin silicon layer (10) overlying the SOI structure. The doping in the gate and body regions is controlled to form lightly doped regions above and below the dielectric, thus defining the active region (16) of the device. Advantageously, the optical electric field essentially coincides with the free carrier concentration area in this active device region. The application of a modulation signal thus causes the simultaneous accumulation, depletion or inversion of free carriers on both sides of the dielectric at the same time, resulting in high speed operation.

    Abstract translation: 基于硅的电光调制器(30)基于形成第一导电性的栅极区域以部分地超过第二导电类型的体区,其中相对薄的电介质层(10)插入在第二导电类型的邻接部分之间 门和身体区域(12,10)。 调制器可以形成在SOI平台上,其中主体区域形成在SOI结构的相对薄的硅表面层中,并且栅极区域由覆盖在SOI结构上的相对薄的硅层(10)形成。 控制栅极和体区中的掺杂以形成电介质上方和下方的轻掺杂区域,从而限定器件的有源区(16)。 有利地,光电场基本上与该有源器件区域中的自由载流子浓度区域重合。 因此,调制信号的应用同时导致电介质两侧的自由载流子的同时累积,消耗或反转,导致高速运行。

    SOI-BASED INVERSE NANOTAPER OPTICAL DETECTOR
    35.
    发明申请
    SOI-BASED INVERSE NANOTAPER OPTICAL DETECTOR 审中-公开
    基于SOI的反相裸片光学检测器

    公开(公告)号:WO2008115194A2

    公开(公告)日:2008-09-25

    申请号:PCT/US2007014102

    申请日:2007-06-13

    CPC classification number: H01L31/03529 H01L31/103 Y02E10/50

    Abstract: A photodetector integrated within a silicon-on-insulator (SOI) structure is formed directly upon an inverse nanotaper endface coupling region to reduce polarization sensitivity at the detector's input. The photodetector may be germanium -based PN (PIN) junction photodetector, a SiGe photodetector, a metal/silicon Schottky barrier photodetector, or any other suitable silicon-based photodetector. The inverse nanotaper photodetector may also be formed as an in-line monitoring device, converting only a portion of the in-coupled optical signal and allowing for the remainder to thereafter propagate along an associated optical waveguide.

    Abstract translation: 集成在绝缘体上硅(SOI)结构中的光电检测器直接形成在反向纳米锥端面耦合区域上,以降低检测器输入处的偏振灵敏度。 光电检测器可以是基于锗的PN(PIN)结光电检测器,SiGe光电检测器,金属/硅肖特基势垒光电检测器或任何其它合适的基于硅的光电检测器。 反向纳米锥光电检测器也可以形成为在线监测装置,仅转换一部分耦合内的光信号,并允许其余部分随后沿相关联的光波导传播。

    ACTIVE MANIPULATION OF LIGHT IN A SILICON-ON-INSULATOR (SOI) STRUCTURE
    37.
    发明申请
    ACTIVE MANIPULATION OF LIGHT IN A SILICON-ON-INSULATOR (SOI) STRUCTURE 审中-公开
    硅绝缘体(SOI)结构中的光的主动操纵

    公开(公告)号:WO2005082091A3

    公开(公告)日:2007-03-22

    申请号:PCT/US2005006365

    申请日:2005-02-28

    CPC classification number: G02B6/12004 G02F1/025 G02F1/292 G02F2001/294

    Abstract: An arrangement for actively controlling, in two dimensions, the manipulation of light within an SOI-based optical structure utilizes doped regions formed within the SOI layer and a polysilicon layer of a silicon-insulator-silicon capacitive (SISCAP) structure. The regions are oppositely doped so as to form an active device, where the application of a voltage potential between the oppositely doped regions functions to modify the refractive index in the affected area and alter the properties of an optical signal propagating through the region. The doped regions may be advantageously formed to exhibit any desired "shaped" (such as, for example, lenses, prisms, Bragg gratings, etc.), so as to manipulate the propagating beam as a function of the known properties of these devices. One or more active devices of the present invention may be included within a SISCAP formed, SOI-based optical element (such as, for example, a Mach-Zehnder interferometer, ring resonator, optical switch, etc.) so as to form an active, tunable element.

    Abstract translation: 用于主动地控制SOI基光学结构内的光的操纵的布置利用形成在SOI层内的掺杂区域和硅绝缘体 - 硅电容(SISCAP)结构的多晶硅层。 这些区域相反地掺杂以形成有源器件,其中在相对掺杂区域之间施加电压电位用于改变受影响区域中的折射率并改变传播通过该区域的光信号的特性。 可以有利地形成掺杂区域以呈现任何期望的“成形”(例如,透镜,棱镜,布拉格光栅等),以便根据这些器件的已知特性来操纵传播光束。 本发明的一个或多个有源器件可以包括在形成SISCAP的SOI基光学元件(例如,诸如Mach-Zehnder干涉仪,环形谐振器,光学开关等)中,以形成活跃的 ,可调元素。

    ARRANGEMENTS FOR REDUCING WAVELENGTH SENSITIVITY IN PRISM-COUPLED SOI-BASED OPTICAL SYSTEMS
    39.
    发明申请
    ARRANGEMENTS FOR REDUCING WAVELENGTH SENSITIVITY IN PRISM-COUPLED SOI-BASED OPTICAL SYSTEMS 审中-公开
    在降低耦合的基于SOI的光学系统中降低波长灵敏度的安排

    公开(公告)号:WO2004097902A3

    公开(公告)日:2005-07-07

    申请号:PCT/US2004013128

    申请日:2004-04-28

    CPC classification number: G02B6/12 G02B6/34 G02B6/4206 G02B26/0833

    Abstract: An optical coupling system for use with multiple wavelength optical signals provides improved coupling efficiency between a free-space optical beam and a relatively thin, surface layer of an SOI structure ("SOI layer"), allowing for sufficient coupling efficiency (greater than 50%) over a predetermined wavelength range. An evanescent coupling layer, disposed between a coupling prism and an SOI layer, is particularly configured to improve the coupling efficiency. In one embodiment, the thickness of the evanescent layer is reduced below an optimum value for a single wavelength, the reduced thickness improving coupling efficiency over a predetermined wavelength range around a defined center wavelength. Alternatively, a tapered thickness evanescent coupling layer may be used to improve coupling efficiency (or a combination of reduced thickness and tapered configuration). Optical beam steering can be combined with a modified evanescent coupling layer to control the input beam launch angle and further improve coupling efficiency.

    Abstract translation: 与多波长光信号一起使用的光耦合系统提供了自由空间光束与SOI结构(“SOI层”)相对薄的表面层之间的耦合效率的提高,从而允许足够的耦合效率(大于50% )在预定波长范围内。 设置在耦合棱镜和SOI层之间的消逝耦合层特别地被配置成提高耦合效率。 在一个实施例中,消逝层的厚度降低到单个波长的最佳值以下,减小的厚度提高了围绕规定的中心波长的预定波长范围的耦合效率。 或者,可以使用渐缩的厚度渐逝耦合层来提高耦合效率(或减小的厚度和锥形配置的组合)。 光束转向可以与修改的渐逝耦合层组合,以控制输入光束的发射角度,进一步提高耦合效率。

    VERTICAL STACKING OF MULTIPLE INTEGRATED CIRCUITS INCLUDING SOI-BASED OPTICAL COMPONENTS
    40.
    发明申请
    VERTICAL STACKING OF MULTIPLE INTEGRATED CIRCUITS INCLUDING SOI-BASED OPTICAL COMPONENTS 审中-公开
    多集成电路的垂直叠加包括基于SOI的光学元件

    公开(公告)号:WO2006084237A9

    公开(公告)日:2006-11-09

    申请号:PCT/US2006004108

    申请日:2006-02-04

    CPC classification number: G02B6/42 G02B6/4214 G02B6/43 G02F1/025 H01L31/12

    Abstract: A vertical stack of integrated circuits includes at least one CMOS electronic integrated circuit (IC), an SOI-based opto-electronic integrated circuit structure, and an optical input/output coupling element. A plurality of metalized vias may be formed through the thickness of the stack so that electrical connections can be made between each integrated circuit. Various types of optical input/output coupling can be used, such as prism coupling, gratings, inverse tapers, and the like. By separating the optical and electrical functions onto separate ICs, the functionalities of each may be modified without requiring a re-design of the remaining system. By virtue of using SOI-based opto-electronics with the CMOS electronic ICs, a portion of the SOI structure may be exposed to provide access to the waveguiding SOI layer for optical coupling purposes.

    Abstract translation: 垂直堆叠的集成电路包括至少一个CMOS电子集成电路(IC),基于SOI的光电集成电路结构和光输入/输出耦合元件。 多个金属化通孔可以穿过堆叠的厚度形成,从而可以在每个集成电路之间进行电连接。 可以使用各种类型的光学输入/输出耦合,例如棱镜耦合,光栅,倒锥等。 通过将光功能和电功能分离到单独的IC上,每个功能可以被修改而不需要重新设计剩余的系统。 通过使用具有CMOS电子IC的基于SOI的光电子器件,SOI结构的一部分可以被暴露以提供通向波导SOI层的通路以用于光学耦合目的。

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