公开(公告)号：CA2521660A1

公开(公告)日：2004-11-04

申请号：CA2521660

申请日：2004-04-23

Applicant: SIOPTICAL INC

Inventor： PATHAK SOHAM ,  SHASTRI KALPENDU ,  PATEL VIPULKUMAR ,  GOTHOSKAR PRAKASH ,  GHIRON MARGARET ,  MONTGOMERY ROBERT KEITH ,  YANUSHEFSKI KATHERINE A

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/124 ,  G02B6/125 ,  G02B6/136 ,  G02B6/28 ,  G02F1/00 ,  G02F1/015 ,  G02B1/02

Abstract: A set of planar, two-dimensional optical devices is able to be created in a sub-micron surface layer of an SOI structure, or within a sub-micron thick combination of an SOI surface layer and an overlying polysilicon layer. Conventional masking/etching techniques may be used to form a variety of passive and optical devices in this SOI platform. Various regions of the devices may be doped to form the active device structures. Additionally, the polysilicon layer may be separately patterned to provide a region of effecti ve mode index change for a propagating optical signal.

公开(公告)号：CA2560845A1

公开(公告)日：2005-10-13

申请号：CA2560845

申请日：2005-03-24

Applicant: SIOPTICAL INC

Inventor： GHIRON MARGARET ,  PIEDE DAVID ,  MONTGOMERY ROBERT KEITH ,  PATEL VIPULKUMAR ,  GOTHOSKAR PRAKASH ,  PATHAK SOHAM ,  YANUSHEFSKI KATHERINE A ,  SHASTRI KALPENDU

IPC: G02B6/125 ,  G02B6/12

Abstract: An arrangement for providing optical crossovers between waveguides formed in an SOI-based structure utilize a patterned geometry in the SOI structure tha t is selected to reduce the effects of crosstalk in the area where the signals overlap. Preferably, the optical signals are fixed to propagate along orthogonal directions (or are of different wavelengths) to minimize the effects of crosstalk. The geometry of the SOI structure is patterned to include predetermined tapers and/or reflecting surfaces to direct/shape the propagating optical signals. The patterned waveguide regions within the optical crossover region may be formed to include overlying polysilicon segments to further shape the propagating beams and improve the coupling efficiency of the crossover arrangement.

公开(公告)号：CA2558483A1

公开(公告)日：2005-09-22

申请号：CA2558483

申请日：2005-03-08

Applicant: SIOPTICAL INC

Inventor： GOTHOSKAR PRAKASH ,  PATHAK SOHAM ,  PIEDE DAVID ,  YANUSHEFSKI KATHERINE A ,  GHIRON MARGARET ,  PATEL VIPULKUMAR ,  SHASTRI KALPENDU ,  MONTGOMERY ROBERT KEITH

IPC: G01R31/26

Abstract: A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto-electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.

公开(公告)号：CA2520625A1

公开(公告)日：2004-10-28

申请号：CA2520625

申请日：2004-04-12

Applicant: SIOPTICAL INC

Inventor： SHASTRI KALPENDU ,  YANUSHEFSKI KATHERINE A ,  PATHAK SOHAM ,  GOTHOSKAR PRAKASH ,  GHIRON MARGARET ,  PATEL VIPULKUMAR ,  MONTGOMERY ROBERT KEITH

IPC: G06F9/45 ,  G06F9/455 ,  G06F17/50 ,  H01L20060101

Abstract: A system and method for providing the layout of non-Manhattan shaped integrated circuit elements using a Manhattan layout system utilizes a plurality of minimal sized polygons (e.g., rectangles) to fit within the boundaries of the non-Manhattan element. The rectangles are fit such that at least one vertex of each rectangle coincides with a grid point on the Manhattan layout system. Preferably, the rectangles are defined by using the spacing being adjacent grid points as the height of each rectangle. As the distance between adjacent grid points decreases, the layout better matches t he actual shape of the non-Manhattan element. The system and method then allows for electrical and optical circuit elements to be laid out simultaneously, using the same layout software and equipment.

公开(公告)号：CA2558483C

公开(公告)日：2015-01-06

申请号：CA2558483

申请日：2005-03-08

Applicant: SIOPTICAL INC

Inventor： GOTHOSKAR PRAKASH ,  GHIRON MARGARET ,  MONTGOMERY ROBERT KEITH ,  PATEL VIPULKUMAR ,  SHASTRI KALPENDU ,  PATHAK SOHAM ,  PIEDE DAVID ,  YANUSHEFSKI KATHERINE A

IPC: G01R31/28 ,  G01R31/26

Abstract: A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto~electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.

公开(公告)号：CA2557509C

公开(公告)日：2014-09-30

申请号：CA2557509

申请日：2005-02-28

Applicant: SIOPTICAL INC ,  GHIRON MARGARET ,  GOTHOSKAR PRAKASH ,  MONTGOMERY ROBERT KEITH ,  PATEL VIPULKUMAR ,  PATHAK SOHAM ,  SHASTRI KALPENDU ,  YANUSHEFSKI KATHERINE A

Inventor： GHIRON MARGARET ,  GOTHOSKAR PRAKASH ,  MONTGOMERY ROBERT KEITH ,  PATEL VIPULKUMAR ,  PATHAK SOHAM ,  SHASTRI KALPENDU ,  YANUSHEFSKI KATHERINE A

IPC: G02F1/025 ,  G02B6/12 ,  H01L27/15

Abstract: An arrangement for actively controlling, in two dimensions, the manipulation of light within an SOI-based optical structure utilizes doped regions formed within the SOI layer and a polysilicon layer of a silicon-insulator-silicon capacitive (SISCAP) structure. The regions are oppositely doped so as to form an active device, where the application of a voltage potential between the oppositely doped regions functions to modify the refractive index in the affected area and alter the properties of an optical signal propagating through the region. The doped regions may be advantageously formed to exhibit any desired "shaped" (such as, for example, lenses, prisms, Bragg gratings, etc.), so as to manipulate the propagating beam as a function of the known properties of these devices. One or more active devices of the present invention may be included within a SISCAP formed, SOI-based optical element (such as, for example, a Mach-Zehnder interferometer, ring resonator, optical switch, etc.) so as to form an active, tunable element.

公开(公告)号：DE602004027305D1

公开(公告)日：2010-07-01

申请号：DE602004027305

申请日：2004-11-17

Applicant: SIOPTICAL INC ,  PATEL VIPULKUMAR ,  GHIRON MARGARET ,  GOTHOSKAR PRAKASH ,  MONTGOMERY ROBERT KEITH ,  PATHAK SOHAM ,  PIEDE DAVID ,  SHASTRI KALPENDU ,  YANUSHEFSKI KATHERINE A

Inventor： PATEL VIPULKUMAR ,  GHIRON MARGARET ,  GOTHOSKAR PRAKASH ,  MONTGOMERY ROBERT KEITH ,  PATHAK SOHAM ,  PIEDE DAVID ,  SHASTRI KALPENDU ,  YANUSHEFSKI KATHERINE A

IPC: H01L27/14 ,  G02B6/12 ,  G02B6/122 ,  H01L31/00 ,  H01L31/0224 ,  H01L31/0232 ,  H01L31/0392 ,  H01L31/06 ,  H01L31/108 ,  H01L31/153

公开(公告)号：CA2581451A1

公开(公告)日：2006-01-19

申请号：CA2581451

申请日：2005-06-22

Applicant: SIOPTICAL INC

Inventor： SHASTRI KALPENDU ,  PATHAK SOHAM ,  DAMA BIPIN ,  MOSINSKIS PAULIUS ,  GOTHOSKAR PRAKASH

IPC: G06F17/50 ,  G06F19/00 ,  G06G7/62

Abstract: Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product ("tape out").

公开(公告)号：CA2546555A1

公开(公告)日：2005-06-09

申请号：CA2546555

申请日：2004-11-17

Applicant: SIOPTICAL INC

Inventor： PIEDE DAVID ,  MONTGOMERY ROBERT KEITH ,  PATHAK SOHAM ,  SHASTRI KALPENDU ,  GHIRON MARGARET ,  PATEL VIPULKUMAR ,  YANUSHEFSKI KATHERINE A ,  GOTHOSKAR PRAKASH

IPC: H01L27/14 ,  G02B6/12 ,  G02B6/122 ,  H01L31/00 ,  H01L31/0224 ,  H01L31/0232 ,  H01L31/0392 ,  H01L31/06 ,  H01L31/108 ,  H01L31/153

Abstract: A silicon-based IR photodetector is formed within a silicon-on-insulator (SOI) structure by placing a metallic strip (preferably, a silicide) over a portion of an optical waveguide formed within a planar silicon surface layer (i.e., "planar SOI layer") of the SOI structure, the planar SOI layer comprising a thickness of less than one micron. Room temperature operation of the photodetector is accomplished as a result of the relatively low dark current associated with the SOI-based structure and the ability to use a relatively small surface area silicide strip to collect the photocurrent. The planar SOI layer may be doped, and the geometry of the silicide strip may be modified, as desired, to achieve improved results over prior art silicon-based photodetectors.

公开(公告)号：CA2520972C

公开(公告)日：2010-01-26

申请号：CA2520972

申请日：2004-04-21

Applicant: SIOPTICAL INC

Inventor： PATEL VIPULKUMAR ,  GHIRON MARGARET ,  GOTHOSKAR PRAKASH ,  MONTGOMERY ROBERT KEITH ,  SHASTRI KALPENDU ,  PATHAK SOHAM ,  YANUSHEFSKI KATHERINE A

IPC: H01L21/76 ,  G02B6/12 ,  G02F1/025 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/13 ,  H01L27/146 ,  H01L31/12

Abstract: A conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.