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公开(公告)号：DE69924804T2
公开(公告)日：2006-02-23
申请号：DE69924804
申请日：1999-02-19
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , OKADA TAKAHIRO
Abstract: An intermediate frequency signal of an OFDM signal received by a tuner (2) is multiplied by a carrier wave by a multiplier (3) and a multiplier (4) to thereby generate an OFDM signal in a base band. The OFDM signal in the base band is FFT processed by an FFT circuit (5) and a resultant signal is outputted to a dividing circuit (10) and a pilot signal extracting circuit (8) in an equalizing circuit (13). A pilot signal extracted by the pilot signal extracting circuit (8) is supplied to an interpolating filter (9) and subjected to an interpolating process. An amplitude component and a phase component in the pilot signal are supplied to the dividing circuit (10). The dividing circuit (10) divides the signal input from the FFT circuit (5) by the amplitude and phase supplied from the interpolating filter (9) and a resultant signal is output to a demapping circuit (11). An FFT window circuit (6) detects the length of the guard interval from outputs of the multipliers (3) and (4) and outputs the detection signal to a control circuit (21). The control circuit (21) controls the band width of the interpolating filter (9) in accordance with the length of the input guard interval, thereby suppressing deterioration in the equalizing characteristics by noises.
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公开(公告)号：DE69832657D1
公开(公告)日：2006-01-12
申请号：DE69832657
申请日：1998-04-30
Applicant: SONY CORP
Inventor： HYAKUDAI TOSHIHISA , IKEDA YASUNARI
Abstract: A technique for receiving an OFDM signal is arranged to reproduce correct carriers. I channel data and Q channel data decomposed into subcarrier components by FFT processing are differential-demodulated by a differential demodulation circuit (803) to remove an FFT window phase error and a reproducing carrier phase error. In a further differential demodulation circuit (809), a reproducing carrier frequency error and a phase error dependent on a reproducing clock frequency error are removed and only I-axis data is thereafter output to be stored in a RAM (810) with respect to each symbol. A pilot signal selecting data generation circuit (811) supplies the RAM (810) with data which is prepared by suitably shifting pilot signal selecting data used as a reference. The resulting data read out is accumulated by cumulative addition performed by a cumulative addition circuit (813). A maximum value detection circuit (814) detects a maximum value of the output from the cumulative addition circuit (813), and the amount of shift of the pilot signal selecting data is stored in a reproducing carrier frequency error storage circuit (822). The reproducing carrier frequency error storage circuit (822) outputs the amount of shift corresponding to the maximum value.
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公开(公告)号：DE69615600T2
公开(公告)日：2002-07-11
申请号：DE69615600
申请日：1996-03-29
Applicant: SONY CORP
Inventor： ITO OSAMU , IKEDA YASUNARI , IKEDA TAMOTSU
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公开(公告)号：BR0101473A
公开(公告)日：2001-11-13
申请号：BR0101473
申请日：2001-04-12
Applicant: SONY CORP
Inventor： OKADA TAKAHIRO , MIYATO YOSHIKAZU , IKEDA YASUNARI , IKEDA TAMOTSU
Abstract: The time required for switch the channel can be remarkably curtailed. When broadcasting signals through a plurality of information channels with an OFDM system, the plurality of information channels are multiplexed in the sense of frequency and collectively subjected to IFFT modulation for connected transmission instead of subjecting the plurality of information channels independently to OFDM modulation for transmission. With this arrangement, the efficiency of exploitation of frequencies is improved. According to the invention, the OFDM frames are synchronized for each information channel for the purpose of connected transmission. Then, the OFDM receiver can switch the information channel for signal reception, maintaining the frame synchronizing signals.
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公开(公告)号：BR0101472A
公开(公告)日：2001-11-13
申请号：BR0101472
申请日：2001-04-12
Applicant: SONY CORP
Inventor： OKADA TAKAHIRO , MIYATO YOSHIKAZU , IKEDA YASUNARI , TAMOTSUIKEDA
Abstract: The time required for switch the channel can be remarkably curtailed. When broadcasting signals through a plurality of information channels with an OFDM system, the plurality of information channels are multiplexed in the sense of frequency and collectively subjected to IFFT modulation for connected transmission instead of subjecting the plurality of information channels independently to OFDM modulation for transmission. With this arrangement, the efficiency of exploitation of frequencies is improved. According to the invention, the OFDM frames are synchronized for each information channel for the purpose of connected transmission. Then, the OFDM receiver can switch the information channel for signal reception, maintaining the frame synchronizing signals.
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Patent Agency Ranking
公开(公告)号：BR0008530A
公开(公告)日：2001-11-06
申请号：BR0008530
申请日：2000-02-25
Applicant: SONY CORP , NIPPON KYOKAI
Inventor： IKEDA YASUNARI , HYAKUDAI TOSHIHISA , OKADA TAKAHIRO , IKEDA TAMOTSU , KURODA TORU , IAI NAOHIKO , TSUCHIDA KENICHI , SASAKI MAKOTO
Abstract: A frequency interleaving circuit frequency-interleaves main signals generated according to sound data by parameters set according to frequencies of transmission channels. A sub-signal generating circuit generates sub-signals for transmission control including pilot signals. Mapping circuits modulate the sub-signals by using pseudo-random sequences generated based on initial values of random codes set according to frequencies of transmission channels. The frequency-interleaved main signals and the sub-signals modulated by the mapping circuits are OFDM-modulated. Then, they are converted to the frequencies of the transmission channels. An increase of a dynamic range of transmission signals can be suppressed by controlling the initial values of random codes set.
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公开(公告)号：AU734249B2
公开(公告)日：2001-06-07
申请号：AU6376098
申请日：1998-05-01
Applicant: SONY CORP
Inventor： HYAKUDAI TOSHIHISA , IKEDA YASUNARI
Abstract: A technique for receiving an OFDM signal is arranged to reproduce correct carriers. I channel data and Q channel data decomposed into subcarrier components by FFT processing are differential-demodulated by a differential demodulation circuit (803) to remove an FFT window phase error and a reproducing carrier phase error. In a further differential demodulation circuit (809), a reproducing carrier frequency error and a phase error dependent on a reproducing clock frequency error are removed and only I-axis data is thereafter output to be stored in a RAM (810) with respect to each symbol. A pilot signal selecting data generation circuit (811) supplies the RAM (810) with data which is prepared by suitably shifting pilot signal selecting data used as a reference. The resulting data read out is accumulated by cumulative addition performed by a cumulative addition circuit (813). A maximum value detection circuit (814) detects a maximum value of the output from the cumulative addition circuit (813), and the amount of shift of the pilot signal selecting data is stored in a reproducing carrier frequency error storage circuit (822). The reproducing carrier frequency error storage circuit (822) outputs the amount of shift corresponding to the maximum value.
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公开(公告)号：AU2942300A
公开(公告)日：2000-10-04
申请号：AU2942300
申请日：2000-03-10
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , IKEDA TAMOTSU , OKADA TAKAHIRO
Abstract: Influence from an adjacent signal is prevented even if a guard band is not provided. A phase comparison unit 21 compares a reference window signal input to a PLL circuit 4 and a window signal supplied from a frequency division circuit 22 and outputs the comparison result to an LPF 23 . The LPF 23 extracts a low frequency component from the input signal and outputs the same to a voltage controlled oscillator 24 . The signal output from the voltage controlled oscillator 24 is supplied as a clock to units of an OFDM modulation circuit 2 and, at the same time, supplied to the frequency division circuit 22 . The frequency division circuit 22 divides the frequency of the supplied signal to thereby generate a new window signal and supplies the same to an IFFT unit 13 . Further, the generated window signal is supplied to a PLL circuit 5 . The PLL circuit 5 generates a clock for controlling a frequency modulation circuit 3 based on the supplied window signal.
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公开(公告)号：AU2942200A
公开(公告)日：2000-09-28
申请号：AU2942200
申请日：2000-03-10
Applicant: SONY CORP
Inventor： IKEDA YASUNARI , HYAKUDAI TOSHIHISA , OKADA TAKAHIRO , IKEDA TAMOTSU
Abstract: A digital broadcast receiving apparatus for receiving a broadcast signal generated by combining sub signals modulated using a random sequence generated based on an initial value set in accordance with a frequency of a broadcast channel by a signal transmission control use signal and a main signal generated based on information source data and reproducing the information source data contained in the received broadcast signal.
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公开(公告)号：AU6376098A
公开(公告)日：1998-11-05
申请号：AU6376098
申请日：1998-05-01
Applicant: SONY CORP
Inventor： HYAKUDAI TOSHIHISA , IKEDA YASUNARI
Abstract: A technique for receiving an OFDM signal is arranged to reproduce correct carriers. I channel data and Q channel data decomposed into subcarrier components by FFT processing are differential-demodulated by a differential demodulation circuit (803) to remove an FFT window phase error and a reproducing carrier phase error. In a further differential demodulation circuit (809), a reproducing carrier frequency error and a phase error dependent on a reproducing clock frequency error are removed and only I-axis data is thereafter output to be stored in a RAM (810) with respect to each symbol. A pilot signal selecting data generation circuit (811) supplies the RAM (810) with data which is prepared by suitably shifting pilot signal selecting data used as a reference. The resulting data read out is accumulated by cumulative addition performed by a cumulative addition circuit (813). A maximum value detection circuit (814) detects a maximum value of the output from the cumulative addition circuit (813), and the amount of shift of the pilot signal selecting data is stored in a reproducing carrier frequency error storage circuit (822). The reproducing carrier frequency error storage circuit (822) outputs the amount of shift corresponding to the maximum value.
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