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公开(公告)号:JPS58164392A
公开(公告)日:1983-09-29
申请号:JP4697682
申请日:1982-03-24
Applicant: SONY CORP
Inventor: OKADA TAKAFUMI , IKEDA YASUNARI , TANAKA YUTAKA
Abstract: PURPOSE:To obtain a red and a blue difference signal with a double speed through simple constitution, by sampling a carrier chrominance signal in its original form, and using one AD converter and a memory circuit for double- speed conversion and then performing time-division processing. CONSTITUTION:The carrier chrominance signal obtained from a luminance one- color separating circuit 2 is supplied to the AD converter 8 to be converted into a digital signal. The AD converter 8 outputs the signal for obtaining the red and blue difference signals alternately at a period 5/4fsc to a double-speed conversion part 13. This double-speed conversion part 13 consists of 1H memories 13a and 13b and switch circuits 13c and 13d. At output terminals 15a and 15b of a switch circuit 15, the positive and negative red and blue difference signals appear alternately at the period 5/4fsc and those are processed by inverting circuits 17 and 21 and switch circuits 16 and 20 to obtain the red and blue difference signals after the double-speed conversion.
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公开(公告)号:JPS58161472A
公开(公告)日:1983-09-26
申请号:JP4309082
申请日:1982-03-18
Applicant: SONY CORP
Inventor: OKADA TAKAFUMI , IKEDA YASUNARI , TANAKA YUTAKA , NAKANO HIROSHI
IPC: H04N7/01
Abstract: PURPOSE:To decrease the deterioration in picture quality and resolution, when line flicker is prevented by non-interlace display, by controlling the gain of a video signal of interpolated scanning lines depending on an amount of correlativity of the video signal of the scanning lines before and after the interplated scanning line. CONSTITUTION:In the figure, assuming that a video signal Si of the interlace system as shown in Figure A is applied to an input terminal 1 and the correlativity between a video signal S1 of a scanning line and a video signal S2 of the succeeding scanning line is weak in the video signal Si, for example. In this case, from a changeover switch 5 as shown in Figure B, a video signal SN1 having a double horizontal frequency, in which video signals of each scanning line of the input video signal Si are continuous for two times in the period of 1/2H. In Figure C, the video signal SN1 and a signal delayed by 1/2H are shown, and are applied to a correlation device 12, and the subtraction output is obtained at the output.
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公开(公告)号:JPS5841683B2
公开(公告)日:1983-09-13
申请号:JP2513578
申请日:1978-03-06
Applicant: SONY CORP
Inventor: ISHIGAKI YOSHIO , OKADA TAKAFUMI , MOTOMYA MASAYUKI
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公开(公告)号:JPS5894277A
公开(公告)日:1983-06-04
申请号:JP19199281
申请日:1981-11-30
Applicant: SONY CORP
Inventor: OKADA TAKAFUMI
Abstract: PURPOSE:To improve vertical resolution, by doubling horizontal and vertical deflecting speeds, and displaying an odd field by the first and the second sub- fields, and an even field by the third and the fourth sub-fiels. CONSTITUTION:In case when a video signal of the upper half of an odd field is stored in an address of the upper half of an RAM5, at the point of time of the center of an odd field of an original video signal, read-out is started from the uppermost address of the RAM5 thereafter, and also the video signal of the odd field is written in order in an address of the lower half of the RAM5. Also, since the read-out is executed at a speed of 2 times of write, a read-out address gradually approaches a write address, and at the point of time of the end of the odd field, the write address coincides with the read-out address. By a signal which is read out during this time, a video signal of the first sub-field is formed at a speed of 2 times, and also a video signal of a video field of the odd field is stored in the whole of the RAM5. In the same way, the first address of an even field is written in the even field.
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公开(公告)号:JPS5887989A
公开(公告)日:1983-05-25
申请号:JP18585581
申请日:1981-11-19
Applicant: SONY CORP
Inventor: OKADA TAKAFUMI , TANAKA YUTAKA
Abstract: PURPOSE:To avoid the resolution from being deteriorated apparently even with a magnified screen, by converting a luminance signal into a double frequency luminance signal and applying it to a matrix circuit. CONSTITUTION:A signal video-detected is separated into a luminance signal Y and a chroma signal Cr at a separation circuit 7. The separated luminance signal Y is applied to a double frequency converting circuit 6, where the signal is converted into a double frequency luminance signal Y and applied to a matrix circuit 8. As to the chroma signal Cr, a chroma signal converted into low and high frequencies at a multiplication circuit 17 is obtained, and the chroma signal of low-frequency-conversion only is picked up through a low pass filter 18 and applied to the matrix circuit 8 via a double frequency conversion circuit 19, a low pass filter 20, a multiplication circuit 21, a band pass filter 22 and a demodulation circuit 9.
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公开(公告)号:JPS5821871B2
公开(公告)日:1983-05-04
申请号:JP8761175
申请日:1975-07-17
Applicant: SONY CORP
Inventor: OKADA TAKAFUMI , MATSUZAKI ATSUSHI
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公开(公告)号:JPS5816394B2
公开(公告)日:1983-03-31
申请号:JP8125275
申请日:1975-07-01
Applicant: SONY CORP
Inventor: OKADA TAKAFUMI , MATSUZAKI ATSUSHI
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公开(公告)号:JPS5843685A
公开(公告)日:1983-03-14
申请号:JP14283681
申请日:1981-09-10
Applicant: SONY CORP
Inventor: FUJIMURA YASUSHI , OKADA TAKAFUMI , YAMAGIWA KAZUO
Abstract: PURPOSE:To execute viewing and listening of a regular picture and voice of a program, by adding a key signal for descrambling a scrambled signal, to a terminal part of a specified program, and sending it out. CONSTITUTION:When a start signal S1 is detected from a signal applied to an input terminal 15, by a code discriminating circuit 22, each circuit is operated. Subsequently, when a key discriminating circuit S2 is detected and a kind of a key signal S5 of a program is discriminated, a signal S6 is written in a memory 23. Also, a synchronization separating circuit 20 samples signals VD, HD from a scrambled picture signal which is applied to a terminal 16, and drives a timing circuit 21. When this program ends, the memory 23 becomes a write mode of the key signal S5, a demodulating circuit 19 demodulates the FSK-modulated signal S5, and sets it as a key signal of a binary code. This signal is synchronized with a clock through the timing circuit 21, is written in the memory 23, and when write ends, a write stop signal is detected, and the write operation is stopped.
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公开(公告)号:JPS5842383A
公开(公告)日:1983-03-11
申请号:JP14072381
申请日:1981-09-07
Applicant: SONY CORP
Inventor: OKADA TAKAFUMI
Abstract: PURPOSE:To eliminate the titled circuit from being affected with external noise, while the line switching operation is performed, by making correction when the line switching operation is not normally executed. CONSTITUTION:A burst signal S5 obtained from a color signal of the PAL system is given to an input (a) of a switch 33 switchingly controlled with the output of a flip-flop 22 and given to an input (b) with a delay for one horizontal scanning period through a 1H delay line 31. The flip-flop 22 controls the line switching. A phase of an output signal of a contact (c) is detected with a reference demodulation carrier wave S6 of B-Y axis. An output of a phase detection circuit 3 makes the flip-flop 22 inoperative when the line switching is correctly done. When the line switching is not done correctly, the flip-flop 22 is controlled for normal operation.
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公开(公告)号:JPS57111185A
公开(公告)日:1982-07-10
申请号:JP18930280
申请日:1980-12-26
Applicant: SONY CORP
Inventor: OKADA TAKAFUMI , TANAKA YUTAKA
Abstract: PURPOSE:To prevent the flicker and to obtain the satisfactory wobbling effect, by giving the analog weighted average to the video signal of a period corresponding to plural scanning lines and in accordance with the wobbling scan position and accordingly eliminating the sampling of the video signal with the high frequency. CONSTITUTION:Video signals S1, S2 and S3 corresponding to plural scanning lines are applied to the bases of transistors TRs Q9, Q10 and Q11 respectively of an analog weighted average circuit 1. These video signals are mixed in a ratio according to the wobbling scan to deliver an output signal S0 to an output terminal 8. Then pairs TRs Q1/Q2, Q3/Q4, Q5/Q6 and Q7/Q8 having a differential constitution each are provided to the circuit 1. The collectors of TRs Q9, Q10 and Q11 are connected to the common emitters of the pairs TRs Q1/Q2, Q3/Q4 and Q5/Q6, respectively. Then a wobbling signal SW of a sine wave given from a wobbling oscillator 2 is applied to the bases of TRs Q2, Q3, Q6 and Q7. At the same time, the voltage V1 of a power supply 3 is applied to the bases of TRs Q5 and Q8, and the voltage V2 divided by a diode 4 is applied to the bases of TRs Q1 and Q4. Thus the occurrence of flicker is prevented.
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