公开(公告)号：US20200035671A1

公开(公告)日：2020-01-30

申请号：US16518436

申请日：2019-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L27/02 ,  H01L23/525

Abstract: An integrated circuit includes a circuit module storing sensitive data. An electrically conductive body at a floating potential is located in the integrated circuit and holds an initial amount of electric charge. In response to an attack attempting to access the sensitive data, electric charge is collected on the electrically conductive body. A protection circuit is configured to ground an output of the circuit module, and thus preclude access to the sensitive data, in response to collected amount of electric charge on the electrically conductive body differing from the initial amount and exceeding a threshold.

公开(公告)号：US10510503B2

公开(公告)日：2019-12-17

申请号：US14985083

申请日：2015-12-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo ,  Brice Arrazat

IPC: H01H59/00 ,  H01L27/06 ,  H01L21/822 ,  H01H1/00 ,  B81C1/00 ,  H01H57/00 ,  H01L23/522

Abstract: Methods of forming and operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.

公开(公告)号：US20190310389A1

公开(公告)日：2019-10-10

申请号：US16450365

申请日：2019-06-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Yoann Goasduff ,  Virginie Bidal ,  Pascal Fornara

IPC: G01V7/04 ,  H01L21/3213 ,  B81C1/00 ,  H01L49/02 ,  B81B3/00 ,  H01H37/32 ,  H01H37/04 ,  H01L29/423

Abstract: A method of operating a mechanical switching device is disclosed. The switching device includes a housing, an assembly disposed in the housing, and a body. The assembly is thermally deformable and comprises a beam held in two different places by two arms secured to edges of the housing. The beam is remote from the body in a first configuration and in contact with and immobilized by the body in a second configuration. The assembly has the first configuration at a first temperature and the second configuration when one of the arms has a second temperature different from the first temperature. The method includes exposing an arm of the assembly to the second temperature, and releasing the beam using a release mechanism. The release mechanism includes a pointed element comprising a pointed region directed towards the body. The pointed element limits an open crater in a concave part of a projection.

公开(公告)号：US10157720B2

公开(公告)日：2018-12-18

申请号：US14517369

申请日：2014-10-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo ,  Brice Arrazat

IPC: H01H61/02 ,  H01H1/58 ,  H01H9/02 ,  B81B3/00

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

公开(公告)号：US10049991B2

公开(公告)日：2018-08-14

申请号：US15596772

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/522 ,  H01L21/70 ,  H01L21/768 ,  H01L23/52 ,  H01L23/00 ,  H01L23/28 ,  H01L23/528 ,  H01L21/56

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.

公开(公告)号：US10049982B2

公开(公告)日：2018-08-14

申请号：US15596877

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.

公开(公告)号：US20180130881A1

公开(公告)日：2018-05-10

申请号：US15864451

申请日：2018-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/112 ,  H01L29/06 ,  H01L21/762 ,  H01L21/763

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US09780045B2

公开(公告)日：2017-10-03

申请号：US15466396

申请日：2017-03-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Guilhem Bouton

IPC: H01L23/00 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L23/576 ,  G06F17/5068 ,  H01L21/768 ,  H01L21/76838 ,  H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

公开(公告)号：US09640493B2

公开(公告)日：2017-05-02

申请号：US14829292

申请日：2015-08-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Guilhem Bouton

IPC: H01L23/00 ,  H01L21/768 ,  H01L27/02 ,  G06F17/50

CPC classification number: H01L23/576 ,  G06F17/5068 ,  H01L21/768 ,  H01L21/76838 ,  H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

公开(公告)号：US09577116B2

公开(公告)日：2017-02-21

申请号：US14963684

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto Simola ,  Pascal Fornara

IPC: H01L29/866 ,  H01L29/40 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.

Abstract translation: 本发明涉及一种齐纳二极管，其包括具有第一导电类型的阴极区，形成在具有第二导电类型的半导体衬底的表面上。 齐纳二极管包括形成在阴极区下面的具有第二导电类型的阳极区域。 一个或多个沟槽隔离将阴极和阳极区域与衬底的其余部分隔离。 第一导电区域被配置为当经受足够的电压时，产生垂直于阴极和阳极区域之间的界面的第一电场。 第二导电区域被配置为当经受足够的电压时，产生平行于阴极和阳极区域之间的界面的第二电场。