公开(公告)号：EP0975022A1

公开(公告)日：2000-01-26

申请号：EP98120034.8

申请日：1998-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

IPC: H01L21/8239 ,  H01L27/105 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42324

Abstract: The manufacturing method comprises, in sequence, the steps of: depositing an upper layer (43) of polycrystalline silicon; defining the upper layer, obtaining LV gate regions (43a) of low voltage transistors and undefined portions (43); forming LV source and drain regions (55) laterally to the LV gate regions; forming a layer of silicide (57a1, 57a2, 57) on the LV source and drain regions (55), on the LV gate regions (43a), and on the undefined portions (43); defining stack gate regions (43b, 43c) and HV gate regions (43d) of high-voltage transistors; and forming HV source and drain regions (64) and cell regions (65a, 65b).

Abstract translation: 所述制造方法包括，在顺序，下列步骤：多晶硅的上层（43）的存入; ，定义上层，获得低电压晶体管和未定义部分（43）的LV栅极区域（43A）; 形成LV源和漏区（55）尾盘反弹到LV栅极区; 形成硅化物上的LV栅极区域（43A）的LV源和漏区（55）的层（57a1，57a2，57）和上未定义部分（43）; 堆栈限定栅极区域（43B，43C）和高电压晶体管的栅极HV区（43D）; 以及形成HV源和漏区（64）和单元区域（65A，65B）。