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    EEPROM with common control gate and common source for two cells
    1.
    发明公开
    EEPROM with common control gate and common source for two cells 审中-公开
    来自“简明英汉词典”

    公开(公告)号：EP0996161A1

    公开(公告)日：2000-04-26

    申请号：EP98830627.0

    申请日：1998-10-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    Abstract: The electronic device comprises pairs of memory cells (61a, 61b), formed in a same active area (9) of a substrate (2) of semiconductor material. Each cell is formed by a selection transistor (63a, 63b) and by a memory transistor (64a, 64b) of the floating gate and double polysilicon layer type. The memory transistors (64a, 64b) of the coupled cells have control gate regions formed by a single continuous gate region (43c) of semiconductor material extending over the respective floating gate regions (30a, 30b) and on the sides thereof which are reciprocally face-to-face, and on the zone of the substrate (2) accommodating a common source line (28).

    Abstract translation: 电子器件包括形成在半导体材料的衬底（2）的相同有源区域（9）中的成对存储单元（61a，61b）。 每个单元由选择晶体管（63a，63b）和浮置栅极和双多晶硅层类型的存储晶体管（64a，64b）形成。 耦合单元的存储晶体管（64a，64b）具有由半导体材料的单个连续栅极区域（43c）形成的控制栅极区域，该半导体材料在相应的浮动栅极区域（30a，30b）上延伸并且在其侧面上是相互面对的 并且在容纳公共源极线（28）的基板（2）的区域上。

    Method for realizing a multilevel ROM memory in a dual gate CMOS process and corresponding ROM memory cell
    2.
    发明公开
    Method for realizing a multilevel ROM memory in a dual gate CMOS process and corresponding ROM memory cell 有权
    一种用于在双栅极CMOS工艺制备多级ROM存储器和相应ROM存储器单元的过程

    公开(公告)号：EP0991118A1

    公开(公告)日：2000-04-05

    申请号：EP98830583.5

    申请日：1998-10-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

    IPC: H01L21/8246 ,  H01L27/112

    CPC classification number: H01L27/112 ,  H01L27/105 ,  H01L27/11253 ,  H01L27/11293

    Abstract: The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type, which method comprises at least the following steps:

    on a semiconductor substrate, defining respective active areas for transistors of ROM cells (1), electrically erasable non-volatile memory cells, and low- and high-voltage transistors;
    depositing a layer of gate oxide over said active areas;
    depositing a polysilicon layer over the gate oxide layer;
    masking, and then etching, the polysilicon layer to define, by successive steps, respective gate regions of the ROM cells, non-volatile cells, and low- and high-voltage transistors;
    characterized in that it further comprises the following steps:
    masking the polysilicon layer (4) of some of the transistors of the ROM cells (1), and implanting a first dopant species (N) in the active areas (2) of the exposed transistors;
    removing the mask from the polysilicon layer (4), and implanting a second dopant species (P) in said previously covered layer;
    masking and subsequently etching the polysilicon layer to define the gate regions of the ROM cell transistors.

    Abstract translation: 本发明涉及生产在双栅型，该方法包括至少以下步骤中的一个CMOS工艺的ROM型的多级存储器的方法，包括：在半导体基片， - 定义respectivement有源区为ROM单元的晶体管 （1），电可擦除非易失性存储器单元，和低和高电压晶体管; 沉积在所述有源区的栅氧化层; 沉积在栅极氧化物层上的多晶硅层; 掩模，然后蚀刻，对多晶硅层进行定义，通过连续的步骤，所述ROM单元，非易失性单元，和低和高电压晶体管的栅极respectivement区; 其特征在于，这样做是还包括以下步骤：掩盖多晶硅层（4）的一些ROM单元的晶体管的（1），以及植入在有源区域的第一掺杂种类（N）（2）的暴露的晶体管 ; 从多晶硅层（4）除去掩模，并在注入。所述第二掺杂剂物种（P）之前覆盖层; 掩蔽并随后蚀刻所述多晶硅层，以限定所述ROM单元晶体管的栅极区域。

    Method for manufacturing EEPROM with periphery
    3.
    发明授权
    Method for manufacturing EEPROM with periphery 有权
    与外围EEPROM的制造方法

    公开(公告)号：EP1014441B1

    公开(公告)日：2009-08-05

    申请号：EP98830771.6

    申请日：1998-12-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Patelmo, Matteo ,  Vajana, Bruno ,  Dalla Libera, Giovanna ,  Cremonesi, Carlo ,  Galbiati, Nadia

    IPC: H01L21/8239 ,  H01L27/105

    CPC classification number: H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

    Abstract: The step of forming source and drain regions (48', 55') for LV transistors includes the steps of forming sacrificial spacers (101) laterally to LV gate regions (43a); forming LV source and drain regions (55') in a self-aligned manner with the sacrificial spacers (101); removing the sacrificial spacers (101); forming HV gate regions (43d) of HV transistors; forming gate regions (43c) of selection transistors; forming control gate regions (43b) of memory transistors; simultaneously forming LDD regions (48') self-aligned with the LV gate regions (43a), HV source and drain regions (64) self-aligned with the HV gate regions (43d), source and drain regions (65a, 65b) self-aligned with the selection gate region (43c) and floating gate region (27b); depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask (72); anisotropically etching the dielectric layer, to form permanent spacers (52') laterally to the LV gate regions (43a); removing the protection silicide mask (72); and forming silicide regions (75a1, 75a2) on the LV source and drain regions (48', 55') and on the LV gate regions (43a).

    Non-volatile semiconductor memory
    6.
    发明公开
    Non-volatile semiconductor memory 审中-公开
    非易失性半导体存储器

    公开(公告)号：EP1033754A1

    公开(公告)日：2000-09-06

    申请号：EP99830111.3

    申请日：1999-03-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Dalla Libera, Giovanna ,  Patelmo, Matteo ,  Vajana, Bruno ,  Galbiati, Nadia

    IPC: H01L27/115 ,  H01L29/423

    CPC classification number: H01L29/42324 ,  H01L27/115

    Abstract: To increase the facing surface and thus the coupling between the floating gate (10a) and control gate (11a) regions of a memory cell (26a), the floating gate (10a) and control gate (11a) regions have a width which is not constant in different section planes parallel to a longitudinal section plane (50) extending through the source (5) and drain (6) regions of the cell. In particular, the width of the floating gate (10a) and control gate (11a) regions is smallest in the longitudinal section plane (50) and increases linearly in successive parallel section planes moving away from the longitudinal section plane.

    Abstract translation: 为了增加存储单元（26a）的浮置栅极（10a）和控制栅极（11a）区域之间的面对表面以及因此的耦合，浮置栅极（10a）和控制栅极（11a）区域的宽度不是 在平行于延伸通过电池的源极（5）和漏极（6）区域的纵向截面（50）的不同截面中恒定。 特别地，浮动栅极（10a）和控制栅极（11a）区域的宽度在纵向截面（50）中最小，并且在远离纵向截面的连续平行部分平面中线性增加。

    Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors, with salicided junctions
    9.
    发明公开
    Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors, with salicided junctions 有权
    具有EEPROM存储器单元，高压晶体管并与Silizidanschlüssen低压晶体管，以及制造方法中的相同的电子设备

    公开(公告)号：EP0986100A1

    公开(公告)日：2000-03-15

    申请号：EP98830645.2

    申请日：1998-10-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

    IPC: H01L21/8239 ,  H01L27/105

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11529

    Abstract: A method for manufacturing electronic devices, comprising memory cells (72) and LV transistors (70) with salicided junctions, comprising, in sequence, the steps of: depositing an upper layer (43) of polycrystalline silicon; defining the upper layer, obtaining floating gate regions (43b) on first areas, LV gate regions (43a) on second areas (13) of a substrate (2), and undefined regions (43) on the first and third areas of the substrate; forming first cell source regions (49 and 50) laterally to the floating gate regions (43b); forming LV source and drain regions (55) laterally to the LV gate regions; forming a silicide layer (57a1, 57a2, 57) on the LV source and drain regions (55), on the LV gate regions (43a), and on the undefined portions (43); defining HV gate regions (43d) on the third areas, and selection gate regions (43c) on the first areas (14); forming source regions (65a) laterally to the selection gate regions (43c), and source and drain regions (64) laterally to the HV gate regions.

    Abstract translation: 一种用于制造电子器件，其包括存储单元（72）和LV晶体管（70）与金属硅化结，其包括，在序列的方法，下列步骤：多晶硅的上层（43）的存入; ，定义上层，获得浮置栅极上的第一种区域的区域（43B），对在基片上的第一和第三区域一个基板（2）的第二区域（13），以及未定义区（43）LV栅极区域（43A） ; 形成第一单元的源极区（49和50）尾盘反弹到浮栅区域（43B）; 形成LV源和漏区（55）尾盘反弹到LV栅极区; 形成上的LV栅极区域（43A）的LV源和漏区（55）的硅化物层（57a1，57a2，57），并在未定义部分（43）; 在第三区域HV-限定栅区（43D），并在所述第一区域的选择栅极区域（43C）（14）; 形成源极区（65A）尾盘反弹到选择栅极区域（43C），以及源极和漏极区（64）尾盘反弹到HV栅极区域。

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