公开(公告)号：US20250124984A1

公开(公告)日：2025-04-17

申请号：US19002360

申请日：2024-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US20250048631A1

公开(公告)日：2025-02-06

申请号：US18664690

申请日：2024-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Junhyoung Kim ,  Joonyoung Kwon ,  Siwan Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device including a cell array structure and a peripheral circuit structure is provided. The cell array structure includes a first stack structure, a second stack structure on the first stack structure, and a third stack structure on the second stack structure, each of the first to third stack structures including a plurality of word lines, vertical channel structures extending into the first to third stack structures, and a second cell contact plug extending into the first to third stack structures and connected to a second contact plug at an end of a second word line in the second stack structure. The second cell contact plug includes a first horizontal protrusion having a horizontal width that increases discontinuously at a connection portion of the first stack structure and the second stack structure.

公开(公告)号：US20240397715A1

公开(公告)日：2024-11-28

申请号：US18544735

申请日：2023-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonyoung Kwon ,  Junhyoung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device including a substrate having a cell array region and a contact region, a gate stack structure positioned in the cell array region, and including a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked on the substrate, a gate pattern stack structure positioned in the contact region, and including a plurality of gate patterns extending from the plurality of gate electrodes, and a plurality of insulation layers alternately stacked with the plurality of gate patterns, a channel structure penetrating the gate stack structure and extending in a direction crossing or intersecting the substrate, and a gate contact portion in the contact region, and penetrating at least a portion of the gate pattern stack structure to be electrically connected to the gate pattern, the plurality of insulation layers including a first insulation layer and a second insulation layer, the second insulating layer including a material different from a material included in the first insulation layer.

公开(公告)号：US20240332431A1

公开(公告)日：2024-10-03

申请号：US18497363

申请日：2023-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Seo ,  Sukkang Sung ,  Cheonan Lee ,  Sangeun Lee ,  Chanho Lee

IPC: H01L29/861 ,  H01L27/02

CPC classification number: H01L29/8611 ,  H01L27/0248

Abstract: A semiconductor device according to an embodiment of the present inventive concept comprises: a first power supply pad configured to receive a first power supply voltage; a second power supply pad configured to receive a second power supply voltage, the second power supply voltage having a level lower than a level of the first power supply voltage; a signal pad configured to exchange a signal; and a first electrostatic discharge (ESD) diode comprising a first impurity region doped with impurities of a first conductivity type and connected to the first power supply pad, and a second impurity region doped with impurities of a second conductivity type different from the first conductivity type and connected to the signal pad, wherein a lower surface of at least one of the first impurity region and the second impurity region has an uneven structure.

公开(公告)号：US20240284683A1

公开(公告)日：2024-08-22

申请号：US18244429

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Seo ,  Manho Lee ,  Sukkang Sung ,  Cheonan Lee

IPC: H10B80/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06582

Abstract: A nonvolatile memory package includes first nonvolatile memory devices configured to be stacked, second nonvolatile memory devices configured to be stacked, and an interface chip connected to an external device through a bonding channel, connected to one of the first nonvolatile memory devices through a first bonding channel, and connected to one of the second nonvolatile memory devices through a second bonding channel, wherein the interface chip includes input/output pads connected to the bonding channel, first input/output pads connected to the first bonding channel, and second input/output pads connected to the second bonding channel, and wherein, for cross-channel shielding, the first input/output pads and the second input/output pads are alternately arranged for each channel.

公开(公告)号：US12057421B2

公开(公告)日：2024-08-06

申请号：US17470644

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A nonvolatile memory device and a data storage system including the same are provided. The nonvolatile memory device includes: a first structure including at least one first memory plane; and a second structure bonded to the first structure and including at least one second memory plane, wherein the number of the at least one first memory plane included in the first structure is different from the number of the at least one second memory plane included in the second structure.

公开(公告)号：US12009325B2

公开(公告)日：2024-06-11

申请号：US17328176

申请日：2021-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Jiwon Kim ,  Jaeho Ahn ,  Joon-Sung Lim ,  Sukkang Sung

IPC: H01L23/00 ,  G11C16/08 ,  G11C16/10 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L24/08 ,  G11C16/08 ,  G11C16/10 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08135 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

公开(公告)号：US11967574B2

公开(公告)日：2024-04-23

申请号：US17460873

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Hwang ,  Jiwon Kim ,  Jaeho Ahn ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device including a first structure; and a second structure on the first structure, wherein the first structure includes a first substrate; a peripheral circuit on the first substrate; a first insulating layer covering the first substrate and the peripheral circuit; and a first bonding pad on the first insulating layer, the second structure includes a second substrate; a memory cell array on a first surface of the second substrate; a second insulating layer covering the first surface of the second substrate and the memory cell array; a conductive pattern at least partially recessed from a second surface of the second substrate; and a second bonding pad on the second insulating layer, the first bonding pad is in contact with the second bonding pad, and the conductive pattern is spaced apart from the second insulating layer.

公开(公告)号：US11955470B2

公开(公告)日：2024-04-09

申请号：US17229062

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jaeho Ahn ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L23/00 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L25/18 ,  H01L24/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2224/08147 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A semiconductor device includes a first peripheral circuit region comprising a plurality of lower circuitries, a second peripheral circuit region apart from the first peripheral circuit region in a vertical direction, the second peripheral circuit region comprising a plurality of upper circuitries, and a cell region comprising a plurality of word lines, the cell region between the first peripheral circuit region and the second peripheral circuit region in the vertical direction. The plurality of word lines comprise a first word line connected to a first lower circuitry selected from the plurality of lower circuitries and a second word line connected to a first upper circuitry selected from the plurality of upper circuitries.

公开(公告)号：US11935597B2

公开(公告)日：2024-03-19

申请号：US17523337

申请日：2021-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/10 ,  G11C16/26 ,  H01L23/481 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.