公开(公告)号：US12045582B2

公开(公告)日：2024-07-23

申请号：US17351699

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pankaj Gupta ,  Karthik Subburaj ,  Sujaata Ramalingam ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G06F7/49 ,  G06F7/501 ,  G06F17/14

CPC classification number: G06F7/49 ,  G06F7/501 ,  G06F17/142

Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.

公开(公告)号：US20240183968A1

公开(公告)日：2024-06-06

申请号：US18459116

申请日：2023-08-31

Applicant: Texas Instruments Incorporated

Inventor： Sandeep Rao ,  Karthik Subburaj ,  Karthik Ramasubramanian

IPC: G01S13/58 ,  G01S7/35

CPC classification number: G01S13/584 ,  G01S7/352 ,  G01S2013/0254

Abstract: In described examples, a frequency modulated continuous wave (FMCW) radar system comprises a first FMCW device that includes a first processor and a second FMCW device that includes a second processor. The first and second processors respectively receive first and second set of FMCW signals corresponding to a field of view (FOV), and—independently from each other—process the first and second sets of FMCW signals to respectively generate first and second sets of virtual antenna array signals. The second FMCW device transmits the second set of virtual antenna array signals to the first FMCW device. The first processor determines angle of arrival information with respect to one or more objects in the FOV in response to the first and second sets of virtual antenna array signals.

公开(公告)号：US11927690B2

公开(公告)日：2024-03-12

申请号：US17574680

申请日：2022-01-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tom Altus ,  Jasbir Singh Nayyar ,  Karthik Ramasubramanian ,  Brian Paul Ginsburg

IPC: G01S7/35 ,  G01S13/34

CPC classification number: G01S7/35 ,  G01S13/34 ,  G01S13/343

Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

公开(公告)号：US11927689B2

公开(公告)日：2024-03-12

申请号：US17351750

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata Ramalingam ,  Karthik Subburaj ,  Pankaj Gupta ,  Anil Varghese Mani ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G01S7/292 ,  G01S7/40 ,  G01S13/524

CPC classification number: G01S7/2922 ,  G01S7/4004 ,  G01S13/5246

Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.

公开(公告)号：US20230204717A1

公开(公告)日：2023-06-29

申请号：US17862738

申请日：2022-07-12

Applicant: Texas Instruments Incorporated

Inventor： Karthik Subburaj ,  Shankar Narayanamoorthy ,  Karthik Ramasubramanian ,  Anand Gadiyar ,  Dheeraj Kumar Shetty ,  Shailesh Joshi

IPC: G01S7/40

CPC classification number: G01S7/40 ,  G01S7/4021 ,  G01S7/4008

Abstract: Methods, apparatus, systems and articles of manufacture to compensate radar system calibration are disclosed. A radio-frequency (RF) subsystem having a transmit channel, a receive channel, and a loopback path comprising at least a portion of the transmit channel and at least a portion of the receive channel, a loopback measurer to measure a first loopback response of the RF subsystem for a first calibration configuration of the RF subsystem, and to measure a second loopback response of the RF subsystem for a second calibration configuration of the RF subsystem, and a compensator to adjust at least one of a transmit programmable shifter or a digital front end based on a difference between the first loopback response and the second loopback response to compensate for a loopback response change when the RF subsystem is changed from the first calibration configuration to the second calibration configuration.

公开(公告)号：US11262435B2

公开(公告)日：2022-03-01

申请号：US15921887

申请日：2018-03-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tom Altus ,  Jasbir Singh Nayyar ,  Karthik Ramasubramanian ,  Brian Paul Ginsburg

IPC: G01S7/35 ,  G01S13/34

Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

公开(公告)号：US20210333357A1

公开(公告)日：2021-10-28

申请号：US17368319

申请日：2021-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram Murali ,  Karthik Subburaj ,  Karthik Ramasubramanian

IPC: G01S7/35 ,  G01S7/40 ,  G01S13/931

Abstract: A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.

公开(公告)号：US20200174884A1

公开(公告)日：2020-06-04

申请号：US16788004

申请日：2020-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Rao ,  Karthik Ramasubramanian ,  Brian Paul Ginsburg

IPC: G06F11/10 ,  G06F3/06 ,  G01S7/35 ,  G01S13/58 ,  G01S13/931 ,  G01S13/34 ,  G01S13/42

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

公开(公告)号：US20190331765A1

公开(公告)日：2019-10-31

申请号：US16442152

申请日：2019-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Rao ,  Karthik Ramasubramanian ,  Indu Prathapan ,  Raghu Ganesan ,  Pankaj Gupta

IPC: G01S7/02 ,  G01S13/58 ,  G01S7/35 ,  G01S13/42 ,  G01S13/34 ,  H04B15/02 ,  H04L27/10

Abstract: A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

公开(公告)号：US20190011533A1

公开(公告)日：2019-01-10

申请号：US16120129

申请日：2018-08-31

Applicant: Texas Instruments Incorporated

Inventor： Brian Paul Ginsburg ,  Karthik Subburaj ,  Karthik Ramasubramanian ,  Sachin Bhardwaj ,  Sriram Murali ,  Sandeep Rao

IPC: G01S7/35 ,  G01S7/02 ,  G01S13/93 ,  G01S7/40 ,  G01S13/32

Abstract: A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF) signal, and an interference monitoring component coupled to the receiver to receive the digital IF signal, in which the interference monitoring component is configured to monitor at least one sub-band in the digital IF signal for interference, in which the at least one sub-band does not include a radar signal.