公开(公告)号：US20230326913A1

公开(公告)日：2023-10-12

申请号：US18334317

申请日：2023-06-13

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri ,  Steven R. Tom ,  Paul Brohlin

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L25/16 ,  H01L23/49838 ,  H01L25/162 ,  H01L23/13 ,  H01L21/4846 ,  H01L23/3736

Abstract: In a described example, an apparatus includes: a first mold compound partially covering a thermal pad that extends through a pre-molded package substrate formed of a first mold compound, a portion of the thermal pad exposed on a die side surface of the pre-molded package substrate, the pre-molded package substrate having a recess on the die side surface, with an exposed portion of the thermal pad and a portion of the first mold compound in a die mounting area in the recess; a semiconductor die mounted to the thermal pad and another semiconductor die mounted to the mold compound in the die mounting area; wire bonds coupling bond pads on the semiconductor dies to traces on the pre-molded package substrate; and a second mold compound over the die side surface of the pre-molded package substrate and covering the wire bonds, the semiconductor dies, the recess, and a portion of the traces.

公开(公告)号：US11636242B2

公开(公告)日：2023-04-25

申请号：US17245253

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ashish Khandelwal ,  Sreenivasan K. Koduri ,  Nikhil Gupta ,  Timothy W. Fischer

IPC: G06F30/27 ,  G06F30/367 ,  G06N3/08 ,  G06N20/00 ,  G06N3/084 ,  G06F30/398 ,  G06F30/337 ,  G06F30/392 ,  G06N20/20 ,  G06F30/373 ,  G06F30/3308 ,  G06F18/2415 ,  G06N3/045 ,  G06F111/20 ,  G06F111/04

Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

公开(公告)号：US11094616B2

公开(公告)日：2021-08-17

申请号：US16543238

申请日：2019-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan K. Koduri ,  Nazila Dadvand

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  C25D7/00 ,  H01L23/31

Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

公开(公告)号：US10985096B2

公开(公告)日：2021-04-20

申请号：US16878576

申请日：2020-05-19

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: In described examples, a terminal (e.g., a conductive terminal) includes a base material, a plating stack and a solder finish. The base material can be a metal, such as copper. The plating stack is arranged on a surface of the base material, and includes breaks in the plating stack. The breaks in the plating stack extend from a first surface of the plating stack to a second surface of the plating stack adjacent to the surface of the base material. The solder finish is coated over the breaks in the plating stack.

公开(公告)号：US20210098406A1

公开(公告)日：2021-04-01

申请号：US16588304

申请日：2019-09-30

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/00

Abstract: A microelectronic device has a die with a die conductor at a connection surface. The microelectronic device includes a pillar electrically coupled to the die conductor, and a head electrically coupled to the pillar. The pillar has a die-side flared end at a die end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by more than a lesser of half a thickness of the die conductor and half a lateral width of the pillar midway between a die end and a head end. The pillar has a head-side flared end at a head end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by a distance that is greater than a lesser of half a thickness of the head and half the lateral width of the pillar. Methods of forming the microelectronic device are disclosed.

公开(公告)号：US10957666B2

公开(公告)日：2021-03-23

申请号：US16151026

申请日：2018-10-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan K. Koduri

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

公开(公告)号：US20200266131A1

公开(公告)日：2020-08-20

申请号：US16867352

申请日：2020-05-05

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Michael Sutton ,  Sreenivasan K. Koduri ,  Subhashish Mukherjee

IPC: H01L23/495

Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.

公开(公告)号：US10734313B2

公开(公告)日：2020-08-04

申请号：US15951021

申请日：2018-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Morroni ,  Rajeev Dinkar Joshi ,  Sreenivasan K. Koduri ,  Sujan Kundapur Manohar ,  Yogesh K. Ramadass ,  Anindya Poddar

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498 ,  H01L25/16 ,  H01L23/50

Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.

公开(公告)号：US20190109105A1

公开(公告)日：2019-04-11

申请号：US16148648

申请日：2018-10-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan K. Koduri

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure having a first width, the first metal layer structure including a first metal layer, the first metal layer electrically coupled to the bond pad. The semiconductor packaging structure also includes a first photosensitive material around sides of the first metal layer structure and a second metal layer structure disposed over the first metal layer structure and over a portion of the first photosensitive material, the second metal layer structure electrically coupled to the first metal layer structure, the second metal layer structure having a second width, where the second width is greater than the first width. Additionally, the semiconductor packaging structure includes a second photosensitive material around sides of the second metal layer structure.

公开(公告)号：US20190109016A1

公开(公告)日：2019-04-11

申请号：US16150986

申请日：2018-10-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan K. Koduri

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth D1 according to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth D2 according to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth D1 is shallower than a height H of the metal strip, and the depth D2 is also shallower than the height H. Other embodiments are presented.