公开(公告)号：US12299364B2

公开(公告)日：2025-05-13

申请号：US17245306

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nikhil Gupta ,  Timothy W. Fischer ,  Ashish Khandelwal ,  Sreenivasan K. Koduri

IPC: G06F30/27 ,  G06F18/2415 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/367 ,  G06F30/373 ,  G06F30/392 ,  G06F30/398 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084 ,  G06N20/00 ,  G06N20/20 ,  G06F111/04 ,  G06F111/20

Abstract: A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

公开(公告)号：US20240297109A1

公开(公告)日：2024-09-05

申请号：US18657689

申请日：2024-05-07

Applicant: Texas Instruments Incorporated

Inventor： Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Sreenivasan K. Koduri

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L21/6835 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/1416 ,  H01L2224/16225 ,  H01L2224/17106 ,  H01L2224/81385 ,  H01L2224/81815

Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

公开(公告)号：US11756914B2

公开(公告)日：2023-09-12

申请号：US17404958

申请日：2021-08-17

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L24/11 ,  H01L2924/01029

Abstract: A microelectronic device has a die with a die conductor at a connection surface. The microelectronic device includes a pillar electrically coupled to the die conductor, and a head electrically coupled to the pillar. The pillar has a die-side flared end at a die end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by more than a lesser of half a thickness of the die conductor and half a lateral width of the pillar midway between a die end and a head end. The pillar has a head-side flared end at a head end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by a distance that is greater than a lesser of half a thickness of the head and half the lateral width of the pillar. Methods of forming the microelectronic device are disclosed.

公开(公告)号：US11430722B2

公开(公告)日：2022-08-30

申请号：US15951003

申请日：2018-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Morroni ,  Rajeev Dinkar Joshi ,  Sreenivasan K. Koduri ,  Sujan Kundapur Manohar ,  Yogesh K. Ramadass ,  Anindya Poddar

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/50

Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

公开(公告)号：US20220208701A1

公开(公告)日：2022-06-30

申请号：US17557372

申请日：2021-12-21

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/00 ,  H01L23/532

Abstract: A method for interconnecting bond pads of semiconductor dies or devices with corresponding leads in a lead frame with printed conductive interconnects in lieu of bond wires and an apparatus resulting from the above method. More specifically, some examples include printing an insulating foundation path from bond-pads on a semiconductor die to leads of a lead frame to which the semiconductor die is attached. A foundation conductive trace is printed on top of the insulating foundation path from each bond pad on the die to a corresponding lead of the lead frame. Optionally, on top of the conductive trace, a cover insulating cover layer is applied on exposed portions of the conductive interconnects and the foundation insulating layer. Preferably, this can be the same material as foundation layer to fully adhere and blend into a monolithic structure, rather than separate layers. Optionally, a protective layer is then applied on the resulting apparatus.

公开(公告)号：US20220189885A1

公开(公告)日：2022-06-16

申请号：US17684251

申请日：2022-03-01

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/14 ,  H01L23/498

Abstract: In a described example, an apparatus includes a packaged device carrier having a board side surface and an opposing surface, the packaged device carrier having conductive leads having a first thickness spaced from one another; the conductive leads having a head portion attached to a dielectric portion, a middle portion extending from the head portion and extending away from the board side surface of the packaged device carrier at an angle to the opposing surface, and each lead having an end extending from the middle portion with a foot portion configured for mounting to a substrate.

公开(公告)号：US20220077014A1

公开(公告)日：2022-03-10

申请号：US17524562

申请日：2021-11-11

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  B81C1/00 ,  B81B3/00 ,  B81B7/00

Abstract: A die-wrapped packaged device includes at least one flexible substrate having a top side and a bottom side that has lead terminals, where the top side has outer positioned die bonding features coupled by traces to through-vias that couple through a thickness of the flexible substrate to the lead terminals. At least one die includes a substrate having a back side and a topside semiconductor surface including circuitry thereon having nodes coupled to bond pads. One of the sides of the die is mounted on the top side of the flexible circuit, and the flexible substrate has a sufficient length relative to the die so that the flexible substrate wraps to extend over at least two sidewalls of the die onto the top side of the flexible substrate so that the die bonding features contact the bond pads.

公开(公告)号：US11177195B2

公开(公告)日：2021-11-16

申请号：US16394564

申请日：2019-04-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan K. Koduri ,  Abram M. Castro

IPC: H01L23/495 ,  H01L23/50

Abstract: In some examples, a device comprises an electronic component having multiple electrical connectors, the multiple electrical connectors configured to couple to a printed circuit board (PCB) and having a first footprint. The device also comprises a multi-lead adapter comprising multiple rows of leads arranged in parallel, the leads in the rows configured to couple to the electrical connectors of the electronic component and having a second footprint that has a different size than the first footprint.

公开(公告)号：US20210249336A1

公开(公告)日：2021-08-12

申请号：US17242121

申请日：2021-04-27

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Michael Sutton ,  Sreenivasan K. Koduri ,  Subhashish Mukherjee

IPC: H01L23/495

Abstract: A coupling device provides galvanic isolation using a leadframe that is configured to support two integrated circuit chips in a coplanar manner. Each chip contains an inductive coupling coil. The lead frame includes a set of bond pads for attaching bond wires to couple to the two integrated circuit chips. Two separated die attach pads support the two chips. Each die attach pad is configured to support one of the two integrated circuit chips with a plurality of cantilevered fingers.

公开(公告)号：US20210143106A1

公开(公告)日：2021-05-13

申请号：US16680044

申请日：2019-11-11

Applicant: Texas Instruments Incorporated

Inventor： Sreenivasan K. Koduri

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48

Abstract: In a described example, an apparatus includes a packaged device carrier having a board side surface and an opposing surface, the packaged device carrier having conductive leads having a first thickness spaced from one another; the conductive leads having a head portion attached to a dielectric portion, a middle portion extending from the head portion and extending away from the board side surface of the packaged device carrier at an angle to the opposing surface, and each lead having an end extending from the middle portion with a foot portion configured for mounting to a substrate.