公开(公告)号：US12165989B2

公开(公告)日：2024-12-10

申请号：US18295192

申请日：2023-04-03

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

公开(公告)号：US12148556B2

公开(公告)日：2024-11-19

申请号：US17383878

申请日：2021-07-23

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Jonathan Almeria Noquil

IPC: H01L23/498 ,  H01F17/00 ,  H01F27/28 ,  H01F41/04 ,  H01L21/56 ,  H01L23/495 ,  H01L23/522 ,  H05K1/16

Abstract: An electronic device includes a multilevel package substrate, conductive leads, a die, and a package structure. The multilevel package substrate has a first level, a second level, and a third level, each having patterned conductive features and molded dielectric features. The first level includes a first patterned conductive feature with multiple turns that form a first winding. The second level includes a second patterned conductive feature, and the third level includes a third patterned conductive feature with multiple turns that form a second winding. A first terminal of the die is coupled to the first end of the first winding, a second terminal of the die is coupled to the second end of the first winding, and a third terminal of the die is coupled to a first conductive lead. The package structure encloses the first die, the second die, and a portion of the multilevel package substrate.

公开(公告)号：US12040265B2

公开(公告)日：2024-07-16

申请号：US17387794

申请日：2021-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Li Jiang

IPC: H01L23/498 ,  H01L23/13 ,  H01P3/02 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/49822 ,  H01P3/02 ,  H05K1/0243

Abstract: In examples, a semiconductor package comprises a ceramic substrate and a horizontal metal layer covered by the ceramic substrate. The metal layer is configured to carry signals in the 5 GHz to 38 GHz frequency range. The package also includes a vertical castellation on an outer surface of the ceramic substrate, the castellation coupled to the metal layer and having a height ranging from 0.10 mm to 0.65 mm.

公开(公告)号：US20240178155A1

公开(公告)日：2024-05-30

申请号：US18071972

申请日：2022-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Chittranjan Mohan Gupta ,  Rajen Manicon Murugan ,  Jie Chen

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4839 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/16 ,  H01L2224/16235 ,  H01L2924/3025

Abstract: An electronic device includes a multilevel package substrate having a first level, a second level, a third level, a conductive signal trace that extends in the second level, and a conductive box shield that surrounds a portion of the conductive signal trace. The electronic device includes a semiconductor die attached to the multilevel package substrate and having a conductive structure coupled to an end of the conductive signal trace. The electronic device includes a package structure that encloses the semiconductor die and a portion of the multilevel package substrate.

公开(公告)号：US11955479B2

公开(公告)日：2024-04-09

申请号：US16667051

申请日：2019-10-29

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Makarand Ramkrishna Kulkarni

IPC: H01L27/07 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H05K1/02

CPC classification number: H01L27/0733 ,  H01L23/3128 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/17 ,  H05K1/0231 ,  H01L2924/15311 ,  H05K2201/09118

Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

公开(公告)号：US20240063118A1

公开(公告)日：2024-02-22

申请号：US17820020

申请日：2022-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： William Harrison ,  Sylvester Ankamah-Kusi ,  Yiqi Tang ,  Rajen M. Murugan

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L24/13 ,  H01L23/5226 ,  H01L21/76885 ,  H01L2224/13025 ,  H01L2224/13147

Abstract: A semiconductor device is described herein. The semiconductor device generally includes a metal fabrication layer disposed on a substrate. The semiconductor device generally includes a dielectric layer having a first plurality of vias aligned with a first metallization region of the metal fabrication layer and a second plurality of vias aligned with a second metallization region of the metal fabrication layer, the dielectric layer disposed on top of the metal fabrication layer. The semiconductor device generally includes a metal layer disposed on the dielectric layer and having a plurality of metal routings, each of the metal regions disposed over both the first metallization region and the second metallization region, each of the plurality of metal routings have a same width. The semiconductor device generally includes an insulation layer disposed on the metal layer, the insulation layer having a plurality of openings to the metal routings of the metal layer.

公开(公告)号：US20230352850A1

公开(公告)日：2023-11-02

申请号：US18309720

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Harshpreet Singh Phull Bakshi ,  Sylvester Ankamah-Kusi ,  Juan Herbsommer ,  Aditya Nitin Jogalekar

IPC: H01Q21/00 ,  H01Q1/22

CPC classification number: H01Q21/005 ,  H01Q1/2283

Abstract: An example microelectronic device package includes: a multilayer package substrate including a slotted waveguide antenna and having routing conductors, the multilayer package substrate having a device side surface and an opposing board side surface; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to slotted waveguide antenna by the routing conductors; and mold compound covering the semiconductor die, and a portion of the multilayer package substrate.

公开(公告)号：US20230352315A1

公开(公告)日：2023-11-02

申请号：US17733921

申请日：2022-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Juan Alejandro Herbsommer

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L21/486 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L24/16

Abstract: One example includes a method for fabricating a substrate-integrated waveguide (SIW). The method includes forming a first metal layer on a carrier surface. The first metal layer can extend along an axis. The method also includes forming a first metal sidewall extending from a first edge of the first metal layer along the axis and forming a second metal sidewall extending from a second edge of the first metal layer opposite the first edge along the axis to form a trough extending along the axis. The method also includes providing a dielectric material over the first metal layer and over the first and second metal sidewalls. The method further includes forming a second metal layer over the dielectric material and over the first and second metal sidewalls. The second metal layer can extend along the axis to enclose the SIW in all radial directions along the axis.

公开(公告)号：US20230352314A1

公开(公告)日：2023-11-02

申请号：US17733998

申请日：2022-04-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Phuong Minh Vu ,  Sylvester Ankamah-Kusi

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/485 ,  H01L23/3121 ,  H01L23/49838 ,  H01L24/16 ,  H01L21/56 ,  H01L2224/16227

Abstract: Described examples include a method having steps of laying out at least two conductors and modeling conductor current through the at least two conductors to determine a current density in the at least two conductors. The method also has steps of revising the at least two conductors as adjusted conductors to add conductive material to areas of the conductor where the modeling conductor current shows above average current density; fabricating the adjusted conductors; and mounting a die to the adjusted conductors.

公开(公告)号：US11784113B2

公开(公告)日：2023-10-10

申请号：US17233110

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Guangxu Li ,  Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/16227

Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.