公开(公告)号：WO1998019238A1

公开(公告)日：1998-05-07

申请号：PCT/US1997019300

申请日：1997-10-27

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  McCRORY, Duane, J.

IPC: G06F09/46

CPC classification number: G06F9/4881 ,  G06F9/3009 ,  G06F9/5044 ,  G06F2209/483

Abstract: In a heterogenous symmetric multi-processing system, processors from distinct families of processors are integrated on a single platform. The processors are coupled to an implementation specific communication mechanism through family specific bus interface converters. Shared memory and I/O subsystems may be coupled to the implementation specific communication mechanism as well. An operating system maintains separate ready queues for each family of processors. Each ready queue is responsible for scheduling execution of process threads on its associated family of processors. The operating system facilitates execution of both single mode binary code files and mixed mode binary code files. When a thread is created, the operating system determines the initial processor family to associate with the thread based on the binary code stream that the thread will begin executing. The thread is placed in the ready queue of that family. As the thread executes it may require services from another family of processors in order to natively execute the next set of instructions in the binary code file. When services are required, the operating system reschedules those instructions on a processor which executes those instructions natively. Means are provided to return the thread to a processor in the previous family of processors in order to support mixed mode instruction stream subroutine support

Abstract translation: 在异构对称多处理系统中，不同处理器系列的处理器集成在单个平台上。 处理器通过特定于家族的总线接口转换器耦合到实现特定的通信机制。 共享存储器和I / O子系统也可以耦合到实现特定的通信机制。 操作系统为每个处理器系列维护单独的就绪队列。 每个就绪队列负责调度其关联的处理器系列的进程线程的执行。 操作系统便于执行单模二进制代码文件和混合模式二进制代码文件。 当创建线程时，操作系统基于线程将开始执行的二进制代码流来确定初始处理器系列与线程相关联。 线程被放置在该家庭的就绪队列中。 当线程执行时，可能需要来自另一系列处理器的服务，以便本地执行二进制代码文件中的下一组指令。 当需要服务时，操作系统重新安排在本地执行这些指令的处理器上的那些指令。 提供了将线程返回到先前系列处理器中的处理器的手段，以便支持混合模式指令流子程序支持

公开(公告)号：WO1998003917A1

公开(公告)日：1998-01-29

申请号：PCT/US1997012619

申请日：1997-07-18

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  PAUL, Derek, William ,  WILTON, Loren, C. ,  BARKER, Frederick, Joseph

IPC: G06F11/34

CPC classification number: G06F11/3433 ,  G06F11/3419 ,  G06F2201/805 ,  G06F2201/81 ,  G06F2201/88

Abstract: A performance regulator program (22) monitors and controls in real time, the performance level which an application program (21-i) achieves when it is executed on a digital computer (10). With this performance regulator program, any external units (11, 12) which are coupled to the computer are prevented from being overloaded by excessive performance in the application program. Also with this performance regulator program, several models of the application program (21-i) can be easily generated such that each model achieves a different performance level.

Abstract translation: 性能调节器程序（22）实时监视和控制应用程序（21-i）在数字计算机（10）上执行时实现的性能水平。 通过这种性能调节器程序，可以防止耦合到计算机的任何外部单元（11,12）因应用程序中的过多性能而过载。 此外，通过该性能调节器程序，可以容易地生成应用程序（21-i）的几个型号，使得每个型号实现不同的性能水平。

公开(公告)号：WO1997050032A1

公开(公告)日：1997-12-31

申请号：PCT/US1997010896

申请日：1997-06-24

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  MAIMONE, William, D.

IPC: G06F09/46

CPC classification number: G06F9/465 ,  G06F2209/462

Abstract: Disclosed is a method for use in a distributed computing enterprise to provide a client or user with access to a requested object located outside the address space of the user. The disclosed method includes: receiving a request for access to a requested object from a user having a first address space; if the requested object exists and is not active, recreating the requested object in the first address space of the user; and, if the requested object is active, performing one of the following steps. If the requested object is in the first address space, providing to the user a pointer that indicates the address of the requested object in the first address space. If the requested object is not currently in the first address space, effecting a transition of the requested object into an inactive state, and then recreating the requested object in the first address space.

Abstract translation: 公开了一种在分布式计算机企业中用于向客户端或用户提供对位于用户的地址空间之外的被请求对象的访问的方法。 所公开的方法包括：从具有第一地址空间的用户接收对所请求对象的访问请求; 如果所请求的对象存在并且不活动，则在用户的第一地址空间中重新创建所请求的对象; 并且如果所请求的对象是活动的，则执行以下步骤之一。 如果所请求的对象位于第一地址空间中，则向用户提供指示第一地址空间中所请求对象的地址的指针。 如果所请求的对象当前不在第一地址空间中，则将所请求的对象转换为非活动状态，然后在第一地址空间中重新创建所请求的对象。

公开(公告)号：WO1997033234A2

公开(公告)日：1997-09-12

申请号：PCT/US1997002885

申请日：1997-02-25

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  HOTCHKIN, Glenn, Thomas

IPC: G06F15/16

CPC classification number: G06F15/16 ,  G06F13/24

Abstract: The present invention operates in a file server (11) having a peripheral storage subsystem (16) coupled thereto by means of a fibre channel (14). The file server (11) includes an apparatus (12) disposed between the file server (11) and the storage subsystem (16) for adapting fibre channel transmissions to and from an industry standard data (29) bus of the file server (11).

Abstract translation: 本发明在具有借助于光纤通道（14）耦合到其的外围存储子系统（16）的文件服务器（11）中运行。 文件服务器（11）包括设置在文件服务器（11）和存储子系统（16）之间的装置（12），用于使文件服务器（11）的工业标准数据（29）总线适配光纤通道传输， 。

公开(公告)号：WO1997004388A1

公开(公告)日：1997-02-06

申请号：PCT/US1996011939

申请日：1996-07-18

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  DAHL, Curtis, Wayne ,  NEUSS, Daniel, Allen ,  COLLETT, Mark, Steven ,  BSHARAH, Mark, Elliot

IPC: G06F09/46

CPC classification number: G06F15/17381

Abstract: A data processing array (11) is partitioned by electronic control signals into multiple sub-arrays (40-46 of Fig. 2A) which are established and operate independently of each other. In the preferred embodiment, an operator's console (30) is provided for manually selecting the data processing nodes that are in each sub-array (40-46 of fig. 2A)), and a control module (20) is coupled by control channels (31, 32, 33) between the console and the data processing nodes (12). These control channels carry the control signals directly to the data processing nodes (12) without utilizing the input/output channels (from message routing circuits 10) which are intercoupled to form the array (11). One portion of these control signals prevents each node in a sub-array from sending messages on the input/output channels to any node in another sub-array; and another portion of the control signals selects a node in each sub-array as a boot node from which a separate operating system and user programs are loaded without utilizing the input/output channels.

Abstract translation: 数据处理阵列（11）被电子控制信号划分成多个子阵列（图2A的40-46），它们被建立并彼此独立地操作。 在优选实施例中，提供操作员控制台（30），用于手动选择每个子阵列（图2A中的40-46）中的数据处理节点），并且控制模块（20）由控制通道 （31,32,33）在控制台和数据处理节点（12）之间。 这些控制信道将控制信号直接传送到数据处理节点（12），而不用互相耦合形成阵列（11）的输入/输出通道（来自消息路由电路10）。 这些控制信号的一部分防止子阵列中的每个节点将输入/输出通道上的消息发送到另一子阵列中的任何节点; 并且控制信号的另一部分选择每个子阵列中的节点作为启动节点，在其上加载单独的操作系统和用户程序，而不利用输入/输出通道。

公开(公告)号：WO1996036144A1

公开(公告)日：1996-11-14

申请号：PCT/US1996006702

申请日：1996-05-08

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  GIALLORENZI, Thomas, Robert ,  MATOLAK, David, William ,  HARRIS, Johnny, Michael ,  STEAGALL, Robert, William ,  WILLIAMS, Bruce, Howard

IPC: H04J11/00

CPC classification number: H04B1/62 ,  H04B2201/70706 ,  H04J13/0003

Abstract: An electronic data transmission system has a low peak-to-average power ratio by including a transmitter circuit which receives an input signal and in response generates a distorted output signal. This distorted output signal is generated by amplifying the input signal with one particular gain when the input signal is at a maximum magnitude which gives the distorted output signal a corresponding maximum magnitude, and by amplifying the input signal with a larger gain when the input signal is in a predetermined range below the maximum magnitude. The distorted output signal travels over a communication channel to a receiver circuit, which regenerates the input signal by amplifying the distorted output signal with a gain that is the inverse of the gain by which the distorted signal is generated.

Abstract translation: 电子数据传输系统通过包括接收输入信号的发射机电路并且响应于产生失真的输出信号而具有低的峰均功率比。 当输入信号为最大幅度时，通过放大具有一个特定增益的输入信号来产生失真的输出信号，该最大幅度给失真的输出信号相应的最大幅度，并且当输入信号为 在最大幅度以下的预定范围内。 失真的输出信号通过通信信道传播到接收机电路，其通过用与产生失真信号的增益的倒数相反的增益放大失真输出信号来再生输入信号。

公开(公告)号：WO1995034861A1

公开(公告)日：1995-12-21

申请号：PCT/US1995007447

申请日：1995-06-13

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  JAFFA, Brent, Ernest ,  BELL, Wayne, D. ,  GILES, John, Philip

IPC: G06F13/40

CPC classification number: G06F13/385 ,  G06F13/4036

Abstract: A bridge circuit (10) includes a microprocessor (20) having a first I/O port which couples to a SCSI bus (11) and a second I/O port which is coupled through transceivers (21) to an EISA bus (12). Also, the bridge circuit includes an EISA interface controller (22), having control lines (32) coupled to the EISA bus and the transceivers, which enable the microprocessor to request and use the EISA bus in time-shared fashion. In order to achieve a high speed of operation, the bridge circuit further includes a memory module (23), coupled via a private bus (24) to the second I/O port of the microprocessor (20), which sends instructions on the private bus directly to the microprocessor, without generating any signals on the EISA bus. In addition, in order to prevent deadlocks on the private bus, the bridge circuit includes a deadlock prevention circuit (25) which is coupled to the microprocessor (20) and the private bus (24) and the EISA interface controller (22). This deadlock prevention circuit detects the occurrence of a predetermined event (figs. 5, 6, 7) during a series of data transmissions between the microprocessor and the EISA bus. When such detection occurs, the deadlock prevention circuit directs the microprocessor to stop the series data transmission over the EISA bus and private bus before the end of the series; and it directs the microprocessor to not restart the series on the private bus until after the EISA bus is required. Meanwhile, instruction fetches on the private bus do occur.

Abstract translation: 桥接电路（10）包括具有耦合到SCSI总线（11）的第一I / O端口和通过收发器（21）耦合到EISA总线（12）的第二I / O端口的微处理器（20） 。 此外，桥接电路包括具有耦合到EISA总线和收发器的控制线（32）的EISA接口控制器（22），其使得微处理器能够以时间分配的方式请求和使用EISA总线。 为了实现高速操作，桥接电路还包括存储器模块（23），其通过专用总线（24）耦合到微处理器（20）的第二I / O端口，其发送私人指令 总线直接连接到微处理器，而不会在EISA总线上产生任何信号。 此外，为了防止专用总线上的死锁，桥接电路包括耦合到微处理器（20）和专用总线（24）和EISA接口控制器（22）的死锁防止电路（25）。 该死锁防止电路在微处理器和EISA总线之间的一系列数据传输期间检测到预定事件的发生（图5,6,7）。 当这种检测发生时，死锁防止电路引导微处理器在系列结束之前停止EISA总线和专用总线上的串行数据传输; 并且它指示微处理器在专用总线上不重新启动系列，直到需要EISA总线为止。 同时，私人巴士上的指令也会发生。

公开(公告)号：WO1994027225A1

公开(公告)日：1994-11-24

申请号：PCT/US1994005044

申请日：1994-05-09

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  PETERSON, LuVerne, Ray

IPC: G06F13/40

CPC classification number: H03K17/167 ,  G06F13/4077 ,  H03K19/00361

Abstract: An electronic control module (25 of Figs. 1 and 2) reduces ringing in the digital signals on a transmission line (26, 27, 28) which has multiple transmitters (22, 23), receivers (24), and parasitic inductors (L) and capacitors (C) coupled to the line. Preferably, a copy of this control module (25) is provided at each node on the line which has a transmitter and/or receiver. Each copy of the control module has three main parts - a sensing circuit (25a), a pulse generating circuit (25b), and a switching circuit (25c). The sensing circuit (25a) is coupled to the transmission line, and it generates a control signal (CTL) when the digital signal on the transmission line changes from a low voltage to a high voltage. The pulse generating circuit (25b) receives the control signal and responds by generating a single pulse (P1). The switching circuit (25c) receives the pulse and, in response, couples a high supply voltage (+V') to the transmission line while the pulse occurs.

Abstract translation: 电子控制模块（图1和图2的25）减少了具有多个发送器（22,23），接收器（24）和寄生电感器（L）的传输线（26,27,28）上的数字信号的振铃 ）和耦合到该线路的电容器（C）。 优选地，在具有发射机和/或接收机的线路上的每个节点处提供该控制模块（25）的副本。 控制模块的每个副本具有三个主要部分：感测电路（25a），脉冲发生电路（25b）和开关电路（25c）。 感测电路（25a）耦合到传输线，并且当传输线上的数字信号从低电压变为高电压时，其产生控制信号（CTL）。 脉冲发生电路（25b）接收控制信号并通过产生单个脉冲（P1）进行响应。 开关电路（25c）接收脉冲，并且作为响应，在脉冲发生时将高电源电压（+ V'）耦合到传输线。

公开(公告)号：WO1994006079A1

公开(公告)日：1994-03-17

申请号：PCT/US1993007977

申请日：1993-08-25

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  CARLSON, Lewis, Rossland ,  CARVER, John, James, II

IPC: G06F11/00

CPC classification number: G06F11/1497

Abstract: A fault tolerant three port (P1, P2, P3) communications module (CM1 of fig. 1) has two control ports (P1 and P2) for receiving commands from two computers (A and B), and a communications port (P3) for transferring data over a communications channel (CC1) in response to the commands. Each control port includes a select line (e.g. SEL1A) which carries a select signal with true and false states, mode lines (e.g. Mode (0-3)A) which carry codes that represent the commands, and a write line (e.g. WRA) which carries a rspective pulse in sync with each of the codes. The select line, mode lines, and write line of each control port are coupled in the module to a respective inter-processor command decoder (20 of fig. 3) having a lead stage (22) and a trail stage (23). The lead stage detects (22) when a predetermined code (e.g. 1001) occurs on the mode lines and the select signal is false during a first one of the pulses; and, the trail stage (23) generates an output signal (IPC) that indicates the receipt of an inter-processor command for the module if, during a second pulse that immediately folows the first pulse, the compliment (0110) of the predetermined code occurs on the mode lines and the select line is true.

Abstract translation: 一个容错三端口（P1，P2，P3）通信模块（图1的CM1）具有用于从两台计算机（A和B）接收命令的两个控制端口（P1和P2）和一个通信端口 通过通信信道（CC1）响应命令传送数据。 每个控制端口包括携带选择信号具有真实状态和错误状态的选择线（例如SEL1A），模式行（例如，模式（0-3）A），其携带代表命令的代码，以及写入行（例如WRA） 其携带与每个代码同步的可视脉冲。 每个控制端口的选择线，模式线和写入线在模块中耦合到具有引导级（22）和跟踪级（23）的相应的处理器间命令解码器（图3的20）。 当在模式行上发生预定代码（例如1001）时，引导级检测（22），并且在第一个脉冲期间选择信号为假; 并且，如果在立即产生第一脉冲的第二脉冲期间，在步骤（23）中产生指示接收到模块的处理器间命令的输出信号（IPC），则预定码的补码（0110） 发生在模式行上，选择行为true。

公开(公告)号：WO1993023827A1

公开(公告)日：1993-11-25

申请号：PCT/US1993004584

申请日：1993-05-14

Applicant: UNISYS CORPORATION

Inventor： UNISYS CORPORATION ,  STOLIS, Paul ,  VALA, John, D. ,  CATCHPOLE, Clive, E. ,  BAKKER, Johan, P. ,  COPENHAVER, Gary, B. ,  CONCANNON, David, J. ,  ROURKE, Robert, T. ,  VALICE, David, J.

IPC: G07D07/00

CPC classification number: G06K17/00 ,  G06K2007/10485 ,  G06K2017/0038 ,  G07D7/12 ,  G07D7/20 ,  G07D11/0084

Abstract: In a check processing array, an imaging/illumination arrangement for illuminating and imaging checks at one or several imaging-sites as they are rapidly, continuously transported past two or more imaging stations, each station having, as its illumination source, a hollow Lambertian integrating vessel, housing lamps which project a highly uniform, diffuse Lambertian illumination-beam to its respective imaging site.

Abstract translation: 在检查处理阵列中，用于在一个或多个成像位置快速，连续地传送通过两个或更多个成像站的照明和成像检查的成像/照明装置，每个站具有作为其照明源的空心朗伯积分 容器，房屋灯，其投射高度均匀的漫射朗伯照明光束到其各自的成像部位。