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    Semiconductor structure including silicon and oxygen-containing metal layer and process thereof
    31.
    发明授权
    Semiconductor structure including silicon and oxygen-containing metal layer and process thereof 有权
    包括硅和含氧金属层的半导体结构及其工艺

    公开(公告)号：US09384985B2

    公开(公告)日：2016-07-05

    申请号：US14334680

    申请日：2014-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Lin ,  An-Chi Liu ,  Hsiao-Pang Chou

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/51

    CPC classification number: H01L21/28088 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

    Abstract: A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H2O2 with the concentration of 0˜0.5 weight percent (wt. %) is performed to polish the metal layer until the barrier layer on the first dielectric layer is exposed. A second chemical mechanical polishing process including a slurry of H2O2 with the concentration higher than 1 weight percent (wt. %) is performed to polish the barrier layer as well as oxidize a surface of the metal layer remaining in the trench until the first dielectric layer is exposed, thereby a metal oxide layer being formed on the metal layer.

    Abstract translation: 用于抛光和氧化的金属浇口工艺包括以下步骤。 在衬底上形成具有沟槽的第一电介质层。 依次形成阻挡层和金属层以覆盖沟槽和第一介电层。 执行包括浓度为0〜0.5重量％（重量％）的H 2 O 2的浆料的第一化学机械抛光工艺，以抛光金属层直到暴露第一​​介电层上的阻挡层。 执行包括浓度高于1重量％（重量％）的H 2 O 2的浆料的第二化学机械抛光方法以抛光阻挡层以及氧化残留在沟槽中的金属层的表面，直到第一介电层 被暴露，从而在金属层上形成金属氧化物层。

    Semiconductor structure
    32.
    发明授权
    Semiconductor structure 有权
    半导体结构

    公开(公告)号：US09054187B2

    公开(公告)日：2015-06-09

    申请号：US14089771

    申请日：2013-11-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

    IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

    Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

    Abstract translation: 非平面半导体结构包括衬底，衬底上的至少一个翅片结构，鳍覆盖部分的鳍结构和衬底的一部分，使得鳍结构被分成与栅极和源极/漏极堆叠的沟道区域， 漏极区域，覆盖在鳍状结构的源极/漏极区域上的多个外延结构，在鳍状结构的沟道区域和外延结构之间设置凹部，以及形成在侧壁上的间隔物 的栅极和外延结构，其中填充在凹槽中的间隔物的部分与外延结构的顶表面齐平。

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    33.
    发明申请
    METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20140113425A1

    公开(公告)日：2014-04-24

    申请号：US13656764

    申请日：2012-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： An-Chi Liu ,  Chun-Hsien Lin

    IPC: H01L21/336

    CPC classification number: H01L21/823412 ,  H01L21/265 ,  H01L21/823425 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/78

    Abstract: A method of fabricating a semiconductor device includes the following steps. At first, at least a gate structure is formed on a substrate. Subsequently, a first material layer and a second material layer sequentially formed on the substrate conformally cover the gate structure. Subsequently, an implantation process is performed on the second material layer, and a wet etching process is further performed to remove a part of the second material layer to form a remaining second material layer. Furthermore, a dry etching process is performed to remove a part of the remaining second material layer to form a partial spacer.

    Abstract translation: 制造半导体器件的方法包括以下步骤。 首先，在基板上形成至少一个栅极结构。 随后，依次形成在基板上的第一材料层和第二材料层共形地覆盖栅极结构。 随后，对第二材料层进行注入工艺，并且进一步执行湿蚀刻工艺以去除第二材料层的一部分以形成剩余的第二材料层。 此外，进行干蚀刻处理以去除剩余的第二材料层的一部分以形成部分间隔物。

    Tunneling field effect transistor and method of fabricating the same
    35.
    发明授权
    Tunneling field effect transistor and method of fabricating the same 有权

    公开(公告)号：US10475892B2

    公开(公告)日：2019-11-12

    申请号：US16172851

    申请日：2018-10-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： An-Chi Liu ,  Chun-Hsien Lin

    IPC: H01L29/423 ,  H01L29/20 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739

    Abstract: A method for forming a tunneling field effect transistor is disclosed, which includes the following steps. First, a semiconductor substrate is provided. A source region is formed on the semiconductor substrate. A tunneling region having a sidewall and a top surface is formed on the source region. A drain region is formed on the tunneling region. A gate dielectric layer is then formed, covering the sidewall and the top surface of the tunneling region. A first metal layer is formed, covering the gate dielectric layer. Subsequently, an anisotropic etching process is performed to remove a portion of the first metal layer. After the anisotropic etching process, a second metal layer is fabricated to cover the remaining first metal layer and the gate dielectric layer.

    Tunneling field effect transistor and method of fabricating the same
    38.
    发明授权
    Tunneling field effect transistor and method of fabricating the same 有权

    公开(公告)号：US10147795B1

    公开(公告)日：2018-12-04

    申请号：US15674526

    申请日：2017-08-11

    Applicant: United Microelectronics Corp.

    Inventor： An-Chi Liu ,  Chun-Hsien Lin

    IPC: H01L21/336 ,  H01L29/78 ,  H03K17/74 ,  H01L29/423 ,  H01L29/417 ,  H01L29/49 ,  H01L29/20 ,  H01L29/66

    Abstract: A tunneling field effect transistor includes a semiconductor substrate, a source region, a tunneling region, a drain region, a gate electrode, and a gate dielectric layer. The source region is disposed on the semiconductor substrate, the tunneling region is disposed on the source region and includes a sidewall and a top surface, the drain region is disposed on the tunneling region, and the gate dielectric layer is disposed between the gate electrode and the tunneling region. The gate electrode is disposed on the source region and the tunneling region and includes a first gate electrode and a second electrode. The first gate electrode is disposed on the sidewall of the tunneling region, and the second gate electrode is disposed on the top surface of the tunneling region. The composition of the first gate electrode is different from the composition of the second gate electrode.

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