公开(公告)号：US20160268311A1

公开(公告)日：2016-09-15

申请号：US14693886

申请日：2015-04-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/24 ,  H01L21/46 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02565 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/84 ,  H01L29/24 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a metal-oxide semiconductor (MOS) transistor thereon, and an oxide semiconductor transistor adjacent to the MOS transistor. Preferably, the MOS transistor includes a first gate structure and a source/drain region adjacent to two sides of the gate structure, and the oxide semiconductor transistor includes a channel layer and the top surface of the channel layer is lower than the top surface of the first gate structure of the MOS transistor.

Abstract translation: 公开了一种半导体器件。 半导体器件包括：其上具有金属氧化物半导体（MOS）晶体管的衬底和与MOS晶体管相邻的氧化物半导体晶体管。 优选地，MOS晶体管包括与栅极结构的两侧相邻的第一栅极结构和源极/漏极区，并且氧化物半导体晶体管包括沟道层，并且沟道层的顶表面低于栅极结构的顶表面 MOS晶体管的第一栅极结构。

公开(公告)号：US20160190019A1

公开(公告)日：2016-06-30

申请号：US15060572

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8238 ,  H01L29/423 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种形成包括衬底，第一晶体管，第二晶体管和第三晶体管的集成电路的方法。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。

公开(公告)号：US09349728B1

公开(公告)日：2016-05-24

申请号：US14670428

申请日：2015-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Bo-Rong Chen

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/8258 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/8258 ,  H01L23/485 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal-oxide semiconductor (MOS) transistor thereon and a first interlayer dielectric (ILD) layer surrounding the MOS transistor; forming a source layer, a drain layer, a first opening between the source layer and the drain layer, and a second ILD layer on the MOS transistor and the first ILD layer, wherein the top surfaces of the source layer, the drain layer, and the second ILD layer are coplanar; forming a channel layer on the second ILD layer, the source layer, and the drain layer and into the first opening; and performing a first planarizing process to remove part of the channel layer so that the top surface of the channel layer is even with the top surfaces of the source layer and the drain layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有金属氧化物半导体（MOS）晶体管的衬底和围绕MOS晶体管的第一层间电介质（ILD）层; 在源极层和漏极层之间形成源极层，漏极层，第一开口以及MOS晶体管和第一ILD层上的第二ILD层，其中源极层，漏极层和 第二ILD层是共面的; 在第二ILD层，源极层和漏极层上形成沟道层并进入第一开口; 并且执行第一平坦化处理以去除沟道层的一部分，使得沟道层的顶表面与源极层和漏极层的顶表面平齐。

公开(公告)号：US09318389B1

公开(公告)日：2016-04-19

申请号：US14520342

申请日：2014-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/82 ,  H01L27/08 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种集成电路，其包括衬底，第一晶体管，第二晶体管和第三晶体管。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。

公开(公告)号：US09196726B2

公开(公告)日：2015-11-24

申请号：US14275858

申请日：2014-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jian-Cun Ke ,  Chih-Wei Yang ,  Chia-Fu Hsu

IPC: H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L29/66575 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/31155 ,  H01L29/4925 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在基板上形成栅极结构; 在衬底中形成轻掺杂漏极; 以及执行用于以平铺方式将氟离子注入所述衬底和所述栅极结构的一部分的第一注入工艺。

公开(公告)号：US10381380B2

公开(公告)日：2019-08-13

申请号：US15947853

申请日：2018-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/22 ,  H01L29/786 ,  H01L27/12 ,  H01L29/51 ,  H01L29/24 ,  H01L23/528 ,  H01L29/66 ,  H01L21/02 ,  H01L21/441 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49

Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. After forming an oxide semiconductor layer on the first insulating layer, two source/drain regions are formed on the oxide semiconductor layer. A bottom oxide layer is formed to entirely cover the source/drain regions, following by forming a high-k dielectric layer on the bottom oxide layer. Next, a thermal process is performed on the high-k dielectric layer, and a plasma treatment is performed on the high-k dielectric layer in the presence of a gas containing an oxygen element.

公开(公告)号：US20170263608A1

公开(公告)日：2017-09-14

申请号：US15604638

申请日：2017-05-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chia-Fu Hsu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/66537 ,  H01L29/66545

Abstract: The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

公开(公告)号：US20170141232A1

公开(公告)日：2017-05-18

申请号：US15368647

申请日：2016-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7869 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer.

公开(公告)号：US09608126B1

公开(公告)日：2017-03-28

申请号：US14953036

申请日：2015-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu ,  Xu Yang Shen ,  Zhibiao Zhou ,  Qinggang Xing

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, an interconnect structure, and an oxide semiconductor structure. The substrate has a first region and a second region. The interconnect structure is disposed on the substrate, in the first region. The oxide semiconductor structure is disposed over a hydrogen blocking layer, in the second region of the substrate.

公开(公告)号：US09543448B1

公开(公告)日：2017-01-10

申请号：US14929396

申请日：2015-11-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种半导体结构，包括基底，图案化氧化物半导体（OS）层，两个源极/漏极区，保护层，栅极层和栅极介电层。 图案化的OS层设置在基底上。 两个源极/漏极区域设置在图案化的OS层上并由凹槽分开。 每个源极/漏极区域包括面向凹部的内侧壁和与内侧壁相对的外侧壁。 保护层设置在图案化的OS层的侧壁上，但不在源/漏区的内侧壁上。 栅极层设置在图案化的OS层上，并且栅极介电层设置在栅极层和图案化的OS层之间。 本发明还提供一种形成该方法的方法。