公开(公告)号：US10756128B2

公开(公告)日：2020-08-25

申请号：US16244109

申请日：2019-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Ko-Wei Lin ,  Chin-Fu Lin ,  Wei-Chuan Tsai ,  Chun-Yao Yang ,  Chia-Fu Cheng ,  Yi-Syun Chou ,  Wei Chen

IPC: H01L27/14 ,  H01L27/146 ,  H01L21/768 ,  H01L49/02

Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

公开(公告)号：US20200212090A1

公开(公告)日：2020-07-02

申请号：US16244109

申请日：2019-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Ko-Wei Lin ,  Chin-Fu Lin ,  Wei-Chuan Tsai ,  Chun-Yao Yang ,  Chia-Fu Cheng ,  Yi-Syun Chou ,  Wei Chen

IPC: H01L27/146 ,  H01L49/02 ,  H01L21/768

Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

公开(公告)号：US20190229053A1

公开(公告)日：2019-07-25

申请号：US15877340

申请日：2018-01-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Jyuan Hung ,  Ai-Sen Liu ,  Bin-Siang Tsai ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L27/01

Abstract: A manufacturing method of a metal-insulator-metal (MIM) capacitor structure includes the following steps. A bottom plate is formed. A first conductive layer is patterned to be the bottom plate, and the first conductive layer includes a metal element. An interface layer is formed on the first conductive layer by performing a nitrous oxide (N2O) treatment on a top surface of the first conductive layer. The interface layer includes oxygen and the metal element of the first conductive layer. A dielectric layer is formed on the interface layer. A top plate is formed on the dielectric layer. The metal-insulator-metal capacitor structure includes the bottom plate, the interface layer disposed on the bottom plate, the dielectric layer disposed on the interface layer, and the top plate disposed on the dielectric layer.

公开(公告)号：US10340391B2

公开(公告)日：2019-07-02

申请号：US15637773

申请日：2017-06-29

Applicant: United Microelectronics Corp.

Inventor： Yen-Chen Chen ,  Xiao Wu ,  Hai Tao Liu ,  Ming Hua Du ,  Shouguo Zhang ,  Yao-Hung Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/10 ,  H01L29/12 ,  H01L21/16 ,  H01L21/44 ,  H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

公开(公告)号：US10121827B1

公开(公告)日：2018-11-06

申请号：US15813173

申请日：2017-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Fu Lin ,  Chung-Yi Chiu

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/16 ,  H01L29/24 ,  H01L29/49 ,  H01L29/786

Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate defining a memory region and a transistor region, an insulating layer is disposed on the substrate, a 2D material layer disposed on the insulating layer, and disposed within the memory and the transistor region, parts of the 2D material layer within the transistor region is used as the channel region of a transistor structure, the transistor structure is disposed on the channel region. And a resistive random access memory (RRAM) located in the memory region, the RRAM includes a lower electrode layer, a resistance transition layer and an upper electrode layer being sequentially located on the 2D material layer and electrically connected to the channel region.

公开(公告)号：US09966425B1

公开(公告)日：2018-05-08

申请号：US15445953

申请日：2017-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chin-Fu Lin ,  Bin-Siang Tsai ,  Xu Yang Shen ,  Seng Wah Liau ,  Yen-Chen Chen ,  Ko-Wei Lin ,  Chun-Ling Lin ,  Kuo-Chih Lai ,  Ai-Sen Liu ,  Chun-Yuan Wu ,  Yang-Ju Lu

IPC: H01L21/8242 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L28/60

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

公开(公告)号：US09923095B2

公开(公告)日：2018-03-20

申请号：US15379486

申请日：2016-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC: H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

Abstract: The present invention provides a non-planar FET and a method of manufacturing the same. The non-planar FET includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

公开(公告)号：US09412653B2

公开(公告)日：2016-08-09

申请号：US14817227

申请日：2015-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。

公开(公告)号：US09397189B2

公开(公告)日：2016-07-19

申请号：US14698828

申请日：2015-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Nien-Ting Ho ,  Chien-Chung Huang ,  Chin-Fu Lin

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/263 ,  H01L29/40

CPC classification number: H01L29/4983 ,  H01L21/2633 ,  H01L21/28026 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

公开(公告)号：US20140346616A1

公开(公告)日：2014-11-27

申请号：US14454727

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chien-Hao Chen ,  Wei-Yu Chen ,  Chi-Yuan Sun ,  Ya-Hsueh Hsieh ,  Tsun-Min Cheng

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.

Abstract translation: 半导体结构包括功函数金属层，（功函数）金属氧化物层和主电极。 功函数金属层位于基板上。 （功函数）金属氧化物层位于功函数金属层上。 主电极位于（功函数）金属氧化物层上。 还提供了形成所述半导体结构的半导体工艺。