公开(公告)号：US20240090342A1

公开(公告)日：2024-03-14

申请号：US18511984

申请日：2023-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Ya-Sheng Feng

IPC: H10N50/80 ,  H01L21/768 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01L21/76801 ,  H01L21/76838 ,  H10N50/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

公开(公告)号：US11538813B2

公开(公告)日：2022-12-27

申请号：US16923117

申请日：2020-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin ,  Chien-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L21/285 ,  H01L29/45

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

公开(公告)号：US11488949B1

公开(公告)日：2022-11-01

申请号：US17340119

申请日：2021-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Liang Yeh ,  Jinn-Horng Lai ,  Ching-Wen Hung ,  Chien-Tung Yue ,  Chun-Li Lin

IPC: G06F17/00 ,  H01L27/02 ,  G01R35/00

Abstract: The present invention provides a method of generating dummy patterns and calibration kits, including steps of generating devices-under-test (DUTs) using a point of said chip window layer as reference point in a unit cell, generating calibration kits corresponding to the DUTs using the point as reference point in corresponding unit cells, generating DUT dummy patterns for each DUTs individually in the unit cell, copying the DUT dummy patterns in the unit cell to the corresponding calibration kits in the corresponding unit cells using the point as reference point, and merging all of the unit cell and corresponding unit cells into a final chip layout.

公开(公告)号：US20210249275A1

公开(公告)日：2021-08-12

申请号：US17241704

申请日：2021-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L21/3105 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/522 ,  H01L27/06

Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

公开(公告)号：US11037796B2

公开(公告)日：2021-06-15

申请号：US16692435

申请日：2019-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L21/3105 ,  H01L23/522 ,  H01L23/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/06

Abstract: A manufacturing method of a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

公开(公告)号：US10553576B2

公开(公告)日：2020-02-04

申请号：US15891312

申请日：2018-02-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

Abstract: A method for filling patterns includes the steps of: providing a substrate having a cell region defined thereon; forming main patterns on the substrate and within the cell region; and filling first dummy patterns adjacent to the main patterns. Preferably, each of the first dummy patterns comprises a first length along X-direction between 2 μm to 5 μm and a second length along Y-direction between 3 μm to 5 μm.

公开(公告)号：US20190273117A1

公开(公告)日：2019-09-05

申请号：US16297698

申请日：2019-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H01L27/22 ,  G11C11/16 ,  H01F41/34 ,  H01F10/32 ,  H01L43/12 ,  H01L23/522 ,  H01L43/08 ,  H01L23/528 ,  H01L43/02

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, first plug, a magnetoresistive random access memory (MRAM) structure, a spacer layer, a seal layer and a first conductive pattern. The substrate has a first region and a second region, and the first plug is disposed on a dielectric layer disposed on the substrate, within the first region. The MRAM structure is disposed in the dielectric layer and electrically connected to the first plug. The spacer layer is disposed both within the first region and the second region, to cover the MRAM structure. The seal layer is disposed on the MRAM structure and the first plug, only within the first region. The first conductive pattern penetrates through the seal layer to electrically connect the MRAM structure.

公开(公告)号：US20190081181A1

公开(公告)日：2019-03-14

申请号：US16140551

申请日：2018-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78642 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A vertical MOS transistor includes a substrate having therein a first source/drain region and a first ILD layer. A nanowire is disposed in the first ILD layer. A lower end of the nanowire is in direct contact with the first source/drain region, and an upper end of the nanowire is coupled with a second source/drain region. The second source/drain region includes a conductive layer. A gate electrode is disposed in the first ILD layer. The gate electrode surrounds the nanowire. A contact hole is disposed in the first ILD layer. The contact hole exposes a portion of the first source/drain region. A contact plug is disposed in the contact hole. A second ILD layer covers the first ILD layer.

公开(公告)号：US20190043729A1

公开(公告)日：2019-02-07

申请号：US15698765

申请日：2017-09-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L21/3105 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L21/31053 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/5228 ,  H01L23/564 ,  H01L27/0629 ,  H01L27/088

Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

公开(公告)号：US10141263B2

公开(公告)日：2018-11-27

申请号：US15894940

申请日：2018-02-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Chih-Sen Huang

IPC: H01L29/66 ,  H01L23/535 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L23/485 ,  H01L23/532

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.