公开(公告)号：US08994103B2

公开(公告)日：2015-03-31

申请号：US13938252

申请日：2013-07-10

Applicant: United Microelectronics Corp.

Inventor： Wei-Lin Chen ,  Tseng-Hsun Liu ,  Kuan-Yu Chen ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66704 ,  H01L29/7825

Abstract: A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

Abstract translation: 横向双扩散金属氧化物半导体晶体管器件包括其中形成有至少浅沟槽隔离的衬底，包围衬底中的STI的外延层，栅极和漏极区以及形成在衬底中的源极区 在门的相应两侧。 外延层，源极区和漏极区包括第一导电型。 栅极包括形成在基板上的第一部分和延伸到STI中的第二部分。

公开(公告)号：US08829611B2

公开(公告)日：2014-09-09

申请号：US13629608

申请日：2012-09-28

Applicant: United Microelectronics Corp.

Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/78

CPC classification number: H01L29/0878 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7816

Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 高电压金属氧化物半导体晶体管器件包括其中形成有绝缘区域的衬底，覆盖绝缘区域的一部分并形成在衬底上的栅极，形成在栅极各侧的源极区域和漏极区域 基板，形成在基板中并与栅极部分重叠的主体区域，以及形成在栅极下方并与主体区域相邻的基板中的第一注入区域。 衬底和体区包括第一导电类型。 源极区域，漏极区域和第一注入区域包括第二导电类型。 第一导电类型和第二导电类型彼此互补。