公开(公告)号：US07049231B2

公开(公告)日：2006-05-23

申请号：US10863046

申请日：2004-06-07

Applicant: Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

Inventor： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

IPC: H01L21/00

CPC classification number: H01L21/28525 ,  C23C16/04 ,  C23C16/24 ,  H01L21/28562 ,  H01L21/31604 ,  H01L21/32051 ,  H01L21/76879 ,  H01L28/60 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/7834

Abstract: In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the crystalline region and not the amorphous region. In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. Doped source/drain regions are formed within semiconductive material laterally proximate the gate. Substantially amorphous insulating material is formed over and laterally proximate the gate. The substrate is provided within a chemical vapor deposition reactor. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the source/drain regions and not on substantially amorphous material, and forming elevated source/drains on the doped source/drain regions. In but another aspect, a method of forming a contact to a substrate is disclosed. A contact opening is etched through amorphous insulating material over a node location ultimately comprising an outwardly exposed substantially crystalline surface. Within a chemical vapor deposition reactor, a gaseous precursor comprising silicon is provided under conditions effective to substantially selectively deposit polysilicon on the outwardly exposed crystalline node location surface and not on the insulating material. Capacitor forming methods are also disclosed.

Abstract translation: 在本发明的一个方面，沉积多晶硅的方法包括在化学气相沉积反应器内提供衬底，衬底具有暴露的基本上结晶的区域和暴露的基本无定形区域。 包含硅的气体前体在有效基本上选择性地在结晶区域而非非晶区域上沉积多晶硅的条件下被供给到化学气相沉积反应器。 在另一方面，在衬底上制造场效应晶体管的方法包括形成栅极介电层和半导体材料上的栅极。 掺杂的源极/漏极区域在靠近栅极的半导体材料内形成。 基本上非晶绝缘材料形成在栅极上方和侧向靠近栅极。 衬底设置在化学气相沉积反应器内。 包含硅的气体前体在有效地基本上选择性地在源极/漏极区域上沉积多晶硅而不是基本上无定形材料的条件下被馈送到化学气相沉积反应器，并且在掺杂源极/漏极区上形成升高的源极/漏极。 在另一方面，公开了一种形成与基板的接触的方法。 接触开口在最终包括向外暴露的基本上结晶的表面的节点位置上通过非晶绝缘材料蚀刻。 在化学气相沉积反应器内，在有效地基本上选择性地将多晶硅沉积在外露的晶体结点位置表面而不是在绝缘材料上的条件下提供包含硅的气态前体。 还公开了电容器形成方法。

公开(公告)号：US07037829B2

公开(公告)日：2006-05-02

申请号：US10355667

申请日：2003-01-31

Applicant: Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

Inventor： Ravi Iyer ,  Yongjun Jeff Hu ,  Luan Tran ,  Brent Gilgen

IPC: H01L21/44

CPC classification number: H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/7687 ,  H01L21/76889 ,  H01L23/485 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/90 ,  H01L29/456 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

公开(公告)号：US06951636B2

公开(公告)日：2005-10-04

申请号：US10793880

申请日：2004-03-08

Applicant: Yongjun Jeff Hu ,  Er-Xuan Ping

Inventor： Yongjun Jeff Hu ,  Er-Xuan Ping

IPC: B01J21/08 ,  B01J27/24 ,  B01J37/02 ,  C01B33/12 ,  C01B33/00

CPC classification number: B01J37/0244 ,  B01J21/08 ,  B01J23/40 ,  B01J23/74 ,  B01J27/24 ,  B01J37/0238

Abstract: A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first layer to form a second layer of silica. Additionally, forming a third layer of nitride material over the second layer, and forming a catalyst material over the nitride layer, can be performed before annealing to form a catalyst body.

Abstract translation: 一种通过在衬底上形成半球形晶粒多晶硅的第一层并且氧化至少一部分第一层以形成第二层二氧化硅来形成催化剂体的方法。 此外，在退火之前可以在第二层上形成第三层氮化物材料，并在氮化物层上形成催化剂材料以形成催化剂体。

公开(公告)号：US06930029B2

公开(公告)日：2005-08-16

申请号：US10263921

申请日：2002-10-03

Applicant: Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

Inventor： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L21/285 ,  H01L21/314 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/44

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/3144 ,  H01L21/76202 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/909

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract translation: 在器件结构的高温处理期间，防止在半导体器件结构内形成氧化钛的方法包括形成钝化层以阻止在半导体器件结构的钛/氧化物界面处形成氧化钛。 该方法包括提供至少包括氧化物区域并在氧化物区域的表面上形成钛层的衬底组件。 在形成钛层之前，用包含氮的等离子体处理氧化物区域表面，以形成形成钛层的钝化层。 在衬底组件上进行热处理，其中钝化层在衬底组件的热处理期间基本上抑制氧从氧化物层的扩散。 一般来说，钝化层包含Si x O x N z N z。

公开(公告)号：US06825113B2

公开(公告)日：2004-11-30

申请号：US10327579

申请日：2002-12-20

Applicant: Yongjun Jeff Hu

Inventor： Yongjun Jeff Hu

IPC: H01L2144

CPC classification number: H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are structures and processes which are related to asymmetric, self-aligned silicidation in the fabrication of integrated circuits. A pre-anneal contact stack includes a silicon substrate, a metal source layer such as titanium-rich titanium nitride (TiNx), and a silicon layer. The metal nitride layer is deposited on the substrate by sputtering a target metal reactively in nitrogen and argon ambient. A N:Ar ratio is selected to deposit a uniform distribution of the metal nitride in an unsaturated mode (x

Abstract translation: 公开了与集成电路制造中的不对称，自对准硅化相关的结构和工艺。 预退火接触堆叠包括硅衬底，诸如富钛钛酸盐（TiNx）的金属源层和硅层。 金属氮化物层通过在氮气和氩气环境中反应溅射靶金属而沉积在基板上。 选择N:Ar比以在不透光（x <1）上沉积金属氮化物在硅衬底上的均匀分布。 中间衬底结构被烧结以形成金属硅化物。 金属的硅化物不对称地消耗了比覆盖硅层更少的下层硅。 所得结构是混合金属硅化物/氮化物层，其具有足够的厚度以提供低的薄层电阻而不过度消耗下面的衬底。 选择不饱和（富金属）领域内最大体积电阻率的金属氮化物，以最大化硅化物的不对称性。

公开(公告)号：US06797558B2

公开(公告)日：2004-09-28

申请号：US10050426

申请日：2002-01-15

Applicant: Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

Inventor： Michael Nuttall ,  Er-Xuan Ping ,  Yongjun Jeff Hu

IPC: H01L218242

CPC classification number: H01L21/28525 ,  C23C16/04 ,  C23C16/24 ,  H01L21/28562 ,  H01L21/31604 ,  H01L21/32051 ,  H01L21/76879 ,  H01L28/60 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/7834

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the substantially crystalline capacitor dielectric region, and the polysilicon is formed into a second capacitor electrode.

Abstract translation: 形成电容器的方法包括在衬底上形成第一电容器电极。 在第一电容器电极上形成基本上结晶的电容器电介质层。 具有基本上结晶的电容器介电层的基板设置在化学气相沉积反应器内。 包含硅的气体前体在有效基本上选择性地在基本上结晶的电容器介电区域上沉积多晶硅的条件下被馈送到化学气相沉积反应器，并且多晶硅形成为第二电容器电极。

公开(公告)号：US06759343B2

公开(公告)日：2004-07-06

申请号：US10050639

申请日：2002-01-15

Applicant: Whonchee Lee ,  Yongjun Jeff Hu

Inventor： Whonchee Lee ,  Yongjun Jeff Hu

IPC: H01L21302

CPC classification number: C23F1/28 ,  H01L21/32134 ,  H01L21/76895

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one-step process or a two-step process. In the one-step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two-step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide.

Abstract translation: 用于集成电路制造的蚀刻方法包括在衬底组件上提供金属氮化物层，在金属氮化物层的第一部分上提供钴硅化物的区域，以及在金属氮化物层的第二部分上提供钴区域。 用至少一种包含无机酸和过氧化物的溶液除去钴的区域和金属氮化物层的第二部分。 此外，去除钴的区域和金属氮化物层的第二部分可以包括一步法或两步法。 在一步法中，用包含无机酸和过氧化物的单一溶液除去钴的区域和金属氮化物层的第二部分。 在两步法中，用含有无机酸和过氧化物的第一溶液除去钴的区域，并用含有过氧化物的第二溶液除去金属氮化物层的第二部分。

公开(公告)号：US06750172B2

公开(公告)日：2004-06-15

申请号：US09805203

申请日：2001-03-14

Applicant: Yongjun Jeff Hu ,  Er-Xuan Ping

Inventor： Yongjun Jeff Hu ,  Er-Xuan Ping

IPC: B01J2724

CPC classification number: B01J37/0244 ,  B01J21/08 ,  B01J23/40 ,  B01J23/74 ,  B01J27/24 ,  B01J37/0238

Abstract: A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first layer to form a second layer of silica. Additionally, forming a third layer of nitride material over the second layer, and forming a catalyst material over the nitride layer, can be performed before annealing to form a catalyst body.

Abstract translation: 一种通过在衬底上形成半球形晶粒多晶硅的第一层并且氧化至少一部分第一层以形成第二层二氧化硅来形成催化剂体的方法。 此外，在退火之前可以在第二层上形成第三层氮化物材料，并在氮化物层上形成催化剂材料以形成催化剂体。

公开(公告)号：US06703303B2

公开(公告)日：2004-03-09

申请号：US10405200

申请日：2003-04-01

Applicant: Gary Chen ,  Li Li ,  Yongjun Jeff Hu

Inventor： Gary Chen ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L214763

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/32134

Abstract: Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base, that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract translation: 金属氮化物和金属氮氧化物挤出物通常在金属硅化物上形成。 这些挤压可能导致短路并降低加工产量。 本发明公开了一种选择性地去除这种挤出物的方法。 在一个实施方案中，包含氧化剂和螯合剂的新型湿蚀刻选择性地从存储器阵列中的字线除去挤出物。 在另一个实施例中，湿蚀刻包括基底，其调整蚀刻的pH以相对于字线中的其它物质选择性地去除某些挤出物。 因此，可以使用新的金属硅化物结构来形成新颖的字线和其他类型的集成电路。

公开(公告)号：US06555455B1

公开(公告)日：2003-04-29

申请号：US09146296

申请日：1998-09-03

Applicant: Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

Inventor： Zhongze Wang ,  Li Li ,  Yongjun Jeff Hu

IPC: H01L213205

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/3144 ,  H01L21/76202 ,  H01L21/76895 ,  H01L21/823481 ,  Y10S438/909

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz. The device structure may be subjected to a rapid thermal process in a nitrogen containing atmosphere or, alternatively, an atmosphere devoid of nitrogen.

Abstract translation: 在器件结构的高温处理期间，防止在半导体器件结构内形成氧化钛的方法包括形成钝化层以阻止在半导体器件结构的钛/氧化物界面处形成氧化钛。 该方法包括提供至少包括氧化物区域并在氧化物区域的表面上形成钛层的衬底组件。 在形成钛层之前，用包含氮的等离子体处理氧化物区域表面，以形成形成钛层的钝化层。 在衬底组件上进行热处理，其中钝化层在衬底组件的热处理期间基本上抑制氧从氧化物层的扩散。 通常，钝化层包括SixOyNz。 装置结构可以在含氮气氛中进行快速热处理，或者在没有氮的气氛中进行快速热处理。