Abstract:
Methods of changing a data rate of communication over an interface between a data transmitter and a data receiver are disclosed, wherein the data transmitter is associated with a first processor and transmitting data over the interface and the data receiver is associated with a second processor. The data transmitter transmits and the data receiver receives data over the interface at a first data rate. At the first processor, it is determined to change the first data rate to a second data rate. The data transmitter transmits and the data receiver receives a request to change the first data rate to the second data rate. In response thereto, a response message is transmitted by the data receiver and received by the data transmitter. When the response message comprises an acknowledgement to change the first data rate to the second data rate, the data transmitter transmits and the data receiver receives data over the interface at the second data rate. Corresponding protocol, electronic circuit and electronic device are also enclosed.
Abstract:
In a mobile device operative in a packet switched wireless network, the control logic for handling the PS connection resides inside the modem part of the device when dual-stack operation is required (e.g., PDN connections having PDN types IPv4 and IPv6). This effectively hides how dual-stack IPv4v6 connectivity is implemented towards the relevant 3GPP network. Further, the modem always only uses one and only one network interface, as seen from the IP stack, when it operates in dual-stack mode, regardless of how the underlying PDN connection(s) are set up.
Abstract:
A service provider node (101), and a method therein, for transmitting data packets relating to parts of a service to a communication device (102). The service provider node and the communication device arecommunicatively connected over a communications network (104) and comprised in a communications system (100). The method comprises receiving (205, 302) a signal (S1), which signal comprises an identifier of the communication device requesting a service, an identifier of the requested service, and an agreement comprising information about a previously agreed part of the service. The method comprises further agreeing (303) on an upcoming part of the service requested by the communication device, while transmitting (206, 304) data packets relating to thepreviously agreed part of the service to the communication device, wherein the data packets are transmitted in dependence of the received signal.
Abstract:
A receiver (100) has an ln-phase path (l-path) (101) that delivers a digital l-path signal ϰ 1 (t) and a Quadrature path (Q-path) (103) that delivers a digital Q-path signal ϰ Q (t). The receiver (100) includes a compensation stage (124) arranged to compensate for gain error g and phase error φ between the digital l-path signal ϰ 1 (t) and the digital Q-path signal ϰ Q (t). The compensation stage (124) has a compensation coefficient generation stage (200), a compensation coefficient application stage (202), a gain control stage (208), a relative gradient generation stage (214) and a step parameter generation stage (224). Compensation coefficients W 1,1 , W 1,2 , W 2,1 , W 2,2 applied to the digital l-path signal ϰ 1 (t) and the digital Q-path signal ϰ Q (t) are generated by iteratively updating them using a relative gradient of the compensated digital in-phase signal γ 1 (t) and a compensated digital quadrature signal γ Q (t), and a step parameter μ n , the magnitude of which is adjusted based on a rate of change of the compensation coefficients W 1,1 , W 1,2 , W 2,1 , W 2,2 .
Abstract translation:接收器(100)具有传送数字l路径信号κ1(t)和正交路径(Q路径)(103)的ln相位路径(1路径)(101) 路径信号κQ(t)。 接收器(100)包括补偿级(124),其被配置为补偿数字l路径信号κ1(t)和数字Q路径信号κQ(t)之间的增益误差g和相位误差phi。 补偿级(124)具有补偿系数生成级(200),补偿系数应用级(202),增益控制级(208),相对梯度生成级(214)和步骤参数生成级(224) 。 通过对数字l路径信号κ1(t)和数字Q路径信号κQ(t)施加的补偿系数W1,1,W1,2,W2,1,W2,2通过使用 补偿的数字同相信号γ1(t)和补偿的数字正交信号γQ(t)的相对梯度,以及基于补偿系数的变化率来调整幅度的步长参数mu n W1,1,W1,2,W2,1,W2,2。
Abstract:
An arrangement (400) for a user equipment, UE, is disclosed. The arrangement (400) comprises an acquiring unit (401) configured to acquire neighboring cell information relating to a plurality of neighboring cells. An assignment unit (403) is provided to assign a priority indicator to each neighboring cell based on the neighboring cell information. Also, a measurement unit (404) is provided to perform measurements on the basis of the assigned priority indicators. The arrangement (400) is arranged such that measurements can be performed more frequently for a neighboring cell having a first priority indicator compared with another neighboring cell having a second priority indicator, which second priority indicator is comparatively lower than the first priority indicator. The disclosure also presents corresponding methods, computer program products and devices.
Abstract:
A receiver 10 and method in the receiver for cell search to find an actual base station having a carrier frequency in a radio communications network 1. The receiver detects a first signal representative of a base station 12,14,16,18 by performing slot synchronisation, frame synchronization, cell identification, measurement of a signal quality of the first signal and comparison of the measured signal quality with a first threshold value. When a first signal having a signal quality that is greater than the first threshold value has been detected, the receiver searches for at least one second signal representative of a base station for at least one frequency offset comprised in a set of offsets S3. Further, when one or more second signals are detected, the receiver selects the signal with the highest signal quality, and detects a broadcast radio channel representative of a base station for the selected signal.
Abstract:
The frequency response of a digital filter, such as a pre-emphasis filter in a signal transmitter having a phase-locked loop, is adjusted using interpolation of the filter coefficients, enabling sets of filter coefficients to be pre-computed or generated as needed in the transmitter. The phase error behavior of the digital filter can be significantly improved.
Abstract:
Methods of configuring dynamic memory associated with a processing system, are described. The dynamic memory is configured in a plurality of blocks, the method comprises: a) receiving information relating to a utilisation status of the memory; b) processing the received information to determine at least one first block of the memory that is currently not in use for information storage; and c) configuring the at least one first block to be excluded from an information refresh process.
Abstract:
An embodiment of a voltage regulation circuit includes a DC-DC converter configured to control a first current provided from a source to a load via a first output, and a linear regulator configured to control a second current provided from the source to the load via a second output. The voltage regulation circuit further includes a single control loop configured to receive an output voltage across the load and a first reference voltage. The single control loop is further configured to generate a single error signal between the output voltage across the load and the first reference voltage and to control the DC-DC converter and the linear regulator using the single error signal such that when the single error signal is outside of a predetermined range the DC-DC converter provides the first current to the load and the linear regulator provides the second current to the load simultaneously.
Abstract:
A signal filter (100) comprises a first transferred impedance filter, TIF, (TIF A ) having four differential signal paths (P A,1 , P A,2 , P A,3 , P A,4 ) and a second TIF (TIF B ) having four differential signal paths (P B,1 , P B,2 , P B,3 , P B,4 )- A first differential signal port of the first TIF (32 A ) is coupled to a first differential signal port of the second TIF (32 B ). A first clock generator (12 A ) is arranged to provide first-TIF clock signals (CLK A,I+ , CLK A,Q+ , CLK A,I- , CLK A,Q- ) having four non-overlapping phases for selecting the respective first-TIF differential signal paths (P A,1 , P A,2 , P A,3 , P A,4 ), and a second clock generator (12 B ) is arranged to provide second-TIF clock signals (CLK B,I+ , CLK B,Q+ , CLK B,J- , CLK B,Q- ) having four non-overlapping phases for selecting the respective second-TIF differential signal paths (P B,1 , P B,2 , P B,3 , P B,4 ). The phases of the second-TIF clock signals (CLK B,I+ , CLK B,Q+ , CLK B,I- , CLK B,Q- ) are equal to the phases of the first-TIF clock signals (CLK A,I+ , CLK A,Q+ , CLK A,I- , CLK A,Q- ) delayed by 45 degrees. The first-TIF first, second, third and fourth clock signals (CLK A,I+ , CLK A,Q+ , CLK A,I- , CLK A,Q- -) and the second-TIF first, second, third and fourth clock signals (CLK B,I+ , CLK B,Q+ , CLK B,I- , CLK B,Q- ) have a duty cycle in the range 16.75% to 25%.