公开(公告)号：WO2007089661A2

公开(公告)日：2007-08-09

申请号：PCT/US2007/002298

申请日：2007-01-26

Applicant: SEARETE LLC ,  MANGIONE-SMITH, William, Henry

Inventor： MANGIONE-SMITH, William, Henry

IPC: G06F9/44

CPC classification number: G06F11/1407 ,  G06F1/263 ,  G06F1/3203 ,  G06F1/3296 ,  G06F11/0706 ,  G06F11/0793 ,  G06F11/1405 ,  G06F11/3471 ,  Y02D10/172

Abstract: Embodiments include a system, an apparatus, a device, and a method. An apparatus includes a synchronous circuit including a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The apparatus also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The apparatus includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The apparatus also includes a power supply configured to electrically couple with a portable power source and operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

Abstract translation: 实施例包括系统，装置，装置和方法。 一种装置包括同步电路，其包括由具有第一电力平面电压的第一电力平面供电的第一子电路和由具有第二电力平面电压的第二电力平面供电的第二子电路。 该装置还包括可操作以检测在第一子电路中发生的计算错误的入射的误差检测器。 该装置包括可操作以基于检测到的计算误差的入射来改变第一功率面电压的控制器。 该装置还包括被配置为与便携式电源电耦合并且可操作以响应于控制器向第一电源平面提供至少两个电压中的选定的一个的电源。

公开(公告)号：WO2007089660A2

公开(公告)日：2007-08-09

申请号：PCT/US2007/002296

申请日：2007-01-26

Applicant: SEARETE LLC ,  MANGIONE-SMITH, William, Henry

Inventor： MANGIONE-SMITH, William, Henry

IPC: G06F9/44

CPC classification number: G06F11/1407 ,  G06F1/263 ,  G06F1/3203 ,  G06F1/3296 ,  G06F11/0706 ,  G06F11/0793 ,  G06F11/1405 ,  G06F11/3471 ,  Y02D10/172

Abstract: Embodiments include a system, a device, and a method. A computing system includes a synchronous circuit. The synchronous circuit includes a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The system also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The system further includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The system may include a power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

Abstract translation: 实施例包括系统，设备和方法。 计算系统包括同步电路。 同步电路包括由具有第一电力平面电压的第一电力平面供电的第一子电路和由具有第二电力平面电压的第二电力平面供电的第二子电路。 该系统还包括可操作以检测在第一子电路中发生的计算误差的入射的误差检测器。 该系统还包括控制器，其可操作以基于检测到的计算误差的入射来改变第一功率面电压。 该系统可以包括可操作以响应于控制器向至少两个电压提供选定的一个电压的电源。

公开(公告)号：WO2006127613A2

公开(公告)日：2006-11-30

申请号：PCT/US2006019754

申请日：2006-05-23

Applicant: MARATHON TECHN CORP ,  LEVEILLE PAUL A ,  BISSETT THOMAS D ,  CORBIN STEPHEN S ,  MELNICK JERRY ,  TREMBLAY GLENN A ,  WATANABE SATOSHI ,  KOYAMA KEIICHI

Inventor： LEVEILLE PAUL A ,  BISSETT THOMAS D ,  CORBIN STEPHEN S ,  MELNICK JERRY ,  TREMBLAY GLENN A ,  WATANABE SATOSHI ,  KOYAMA KEIICHI

IPC: G04F8/00

CPC classification number: G06F9/52 ,  G06F11/1405 ,  G06F11/1683 ,  G06F11/1691 ,  G06F11/2038 ,  G06F11/2097 ,  G06F12/1458 ,  G06F12/1483

Abstract: A symmetric multiprocessing fault-tolerant computer system controls memory access in a symmetric multiprocessing computer system. To do so, virtual page structures are created, where the virtual page structures reflect physical page access privileges to shared memory for processors in a symmetric multiprocessing computer system. Access to shared memory is controlled based on physical page access privileges reflected in the virtual paging structures to coordinate deterministic shared memory access between processors in the symmetric multiprocessing computer system. A symmetric multiprocessing fault-tolerant computer system may use duplication or continuous replay.

Abstract translation: 对称多处理容错计算机系统控制对称多处理计算机系统中的存储器访问。 为此，创建了虚拟页面结构，虚拟页面结构反映了对称多处理计算机系统中处理器的共享内存的物理页面访问权限。 基于在虚拟分页结构中反映的物理页面访问权限来控制对共享存储器的访问，以协调对称多处理计算机系统中的处理器之间的确定性共享存储器访问。 对称多处理容错计算机系统可以使用重复或连续重放。

公开(公告)号：EP1369786A3

公开(公告)日：2005-03-23

申请号：EP03252741.8

申请日：2003-04-30

Applicant: Sun Microsystems, Inc.

Inventor： Tremblay, Marc ,  Chaudhry, Shailender ,  Jacobson, Quinn A.

IPC: G06F11/10 ,  G06F11/14 ,  G06F9/38

CPC classification number: G06F11/1032 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1405

Abstract: One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.

公开(公告)号：EP1417582A2

公开(公告)日：2004-05-12

申请号：EP02794621.9

申请日：2002-08-02

Applicant: iRoC Technologies

Inventor： NICOLAIDIS, Michel

IPC: G06F11/14

CPC classification number: G06F9/3869 ,  G06F9/3861 ,  G06F11/1405

Abstract: The invention concerns a circuit (3) for detecting errors in data supplied by at least one of the blocks of the assembly. When an error has been detected, the assembly is decontaminated by means of at least a circuit for backup and reconstitution of past states of a latch associated with a block. The backup and reconstitution circuit comprises a multiplexer (6) and a FIFO buffer register (5). The multiplexer includes a first input directly connected to the output of the latch (2a) and a second input connected to said output via the buffer register. A control circuit (4) controls the buffer register and the multiplexer so as to activate the buffer register writing function and to connect the multiplexer output to its first input at each cycle, during a normal operating phase, and to activate the buffer register reading function and connect the multiplexer output to its second input during predetermined cycles of a decontamination phase.

公开(公告)号：EP1042712A1

公开(公告)日：2000-10-11

申请号：EP98963788.9

申请日：1998-12-04

Applicant: Bull HN Information Systems Inc.

Inventor： YODER, Ronald, W. ,  GUENTHNER, Russell, W. ,  BUZBY, Wayne, R.

IPC: G06F3/00 ,  G06F15/16

CPC classification number: G06F11/1405 ,  G06F9/3863 ,  G06F11/1407

Abstract: In order to gather, store temporarily and efficiently deliver safestore information in a CPU (10) having data manipulation (40) circuitry including a register bank, first and second serially oriented safestore buffers are employed. At suitable times during the processing of information, a copy of the instantaneous contents of the register bank is transferred into the first safestore buffer. After a brief delay, a copy of the first safestore buffer is transferred into the second safestore buffer. If a call for a domain change (42) (which might include a process change or a fault) is sensed, a safestore frame is sent to cache (3), and the first safestore buffer is loaded from the second safestore buffer rather than from the register bank. Later, during a climb operation, if a restart of the interrupted process is undertaken and the restoration of the register bank is directed to be taken from the first safestore buffer, this source, rather than the safestore frame stored in cache (3), is employed to obtain a corresponding increase in the rate of restart. In one embodiment, the transfer of information between the register bank and the safestore buffers is carried out on a bit-by-bit basis to achieve additional flexibility of operation and also to conserve integrated circuit space.

公开(公告)号：EP0681239A3

公开(公告)日：1996-01-24

申请号：EP95111006.3

申请日：1989-12-08

Applicant: TANDEM COMPUTERS INCORPORATED

Inventor： Cutts, Richard W., Jr. ,  Banton, Randall G. ,  Jewett, Douglas E. ,  Norwood, Peter C. ,  Debacker, Kenneth C. ,  Mehta, Nikhil A. ,  Allison, John David ,  Horst, Robert W.

IPC: G06F11/16 ,  G06F11/18

CPC classification number: G06F9/3863 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F11/0724 ,  G06F11/0757 ,  G06F11/1008 ,  G06F11/1405 ,  G06F11/1415 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/18 ,  G06F11/181 ,  G06F11/182 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2015 ,  G06F11/2017 ,  G06F2201/85 ,  G11C29/74

Abstract: This fault-tolerant computer system employs multiple (for example, three) identical CPUs executing the same instruction stream, with multiple (for example, two) memory modules which in their address space of the CPUs store duplicates of the same data. The CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of the others until all execute the respective function simultaneously. Interrupts are synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses. I/O devices are accessed through a pair of redundant identical I/O processors, but only one is designated to actively control a given I/O device. In case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

公开(公告)号：EP0380858B1

公开(公告)日：1994-10-26

申请号：EP89309651.1

申请日：1989-09-22

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： Beaven, Richard C. ,  Evans, Michael B. ,  Hetherington, Ricky C. ,  Fossum, Tryggve

IPC: G06F11/00 ,  G06F11/14

CPC classification number: G06F11/2236 ,  G06F9/3863 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/0781 ,  G06F11/1405

Abstract: In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is identified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.

公开(公告)号：EP0415548A2

公开(公告)日：1991-03-06

申请号：EP90308005.9

申请日：1990-07-20

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： Bruckert, William ,  Kovalcin, David ,  Bissett, Thomas D.

IPC: G06F11/16 ,  G06F9/44

CPC classification number: G06F11/1633 ,  G06F9/4401 ,  G06F11/10 ,  G06F11/1405 ,  G06F11/1604 ,  G06F11/1608 ,  G06F11/1616 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/167 ,  G06F11/1679 ,  G06F15/177 ,  G06F2201/845

Abstract: Method and apparatus for controlling initiating of bootstrap loading in a computer system having first and second discrete computing zones is disclosed. Each computing zone includes a status register for storing an operating system run (OSR) bit indicating that the zone has initiated bootstrap loading. A cable connects the computing zones to allow the first and second zones to read the status registers in the second and first zones, respectively. A CPU in each zone only enables initiation of bootstrap loading if the OSR bit in the other zone is not set.

Abstract translation: 公开了一种用于控制具有第一和第二离散计算区域的计算机系统中引导加载启动的方法和装置。 每个计算区域包括状态寄存器，用于存储指示区域已经启动引导加载的操作系统运行（OSR）位。 电缆连接计算区域，以允许第一和第二区域分别读取第二和第一区域中的状态寄存器。 如果其他区域中的OSR位未设置，每个区域中的CPU只能启动引导加载。

公开(公告)号：EP0380858A2

公开(公告)日：1990-08-08

申请号：EP89309651.1

申请日：1989-09-22

Applicant: DIGITAL EQUIPMENT CORPORATION

Inventor： Beaven, Richard C. ,  Evans, Michael B. ,  Hetherington, Ricky C. ,  Fossum, Tryggve

IPC: G06F11/00 ,  G06F11/14

CPC classification number: G06F11/2236 ,  G06F9/3863 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/0781 ,  G06F11/1405

Abstract: In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is identified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.

Abstract translation: 在多处理器系统中，一个错误在CPU中的任一项发生的可能对操作来影响其余的CPU，因此本文错误必须快速处理。 错误被分为两类：同步的错误（thosethat必须立即纠正，以允许当前指令的继续处理）; 和异步错误（这些错误不影响当前指令的执行做，可能在完成当前指令的执行处理）。 由于同步错误防止继续当前指令的执行，优选做的断层CPU的负荷稳定的状态条件被恢复，且该错误指令重新执行。 这些稳定状态条件下的每个指令的执行之间有利地好发。 然而，在流水线计算机系统中，很难确定一个选择的指令的开始和结束，因为多个指令是在过程中，在Sametime中。 因此，执行单元被选择为错误处理和指令执行之间的同步点。 一旦错误被识别为同步或异步和所述执行单元允许该指令来完成或回滚该状态条件以它们的preinstruction值，错误分析软件检查CPU中的可疑数据锁存器的状态。 串行诊断链路停止CPU的系统时钟和串行加载CPU数据锁存到系统处理器单元对错误确定。 那里以后，CPU的系统时钟是重新启动，并且CPU继续执行。