Abstract:
전기식 제어 발진기 회로와, 이 회로를 구비한 전기식 제어 필터 장치. 전기식 제어 발진기 회로(30)는 평형된 두 상호 콘덕턴스 회로(G1, G2)를 구비하며 이들 회로 각각은 반전기(Inv1 내지 Inv4)와 저항(Inv5 내지 Inv6)으로서 배열된 트랜지스터상을 구비한다. 단일 제어 신호에 의해 발진기 회로(30)의 발진 주파수(f) 및 양호도(Q)를 제어하기 위하여, 결합된 제어 회로(Inv7, Dif, IM1, IM2)가 제공된다. 전류 미러회로(IM1, IM2)와 차동쌍(Dif)에 의하여 양호도(Q)를 조정하기 위한 제어 신호가 주파수(f)를 조정하기 위한 제어 신호에 결합된 저항 연결된 다른 트랜지스터쌍(Inv7)으로부터 파생된다. 제어 회로(Inv7, Dif, IM1, IM2)에 의해 발생된 제어신호에 의해 동일한 상호 콘덕턴스 회로(G3 내지 G9)를 구비한 전기식 제어 필터 장치의 양호도를 조정하기 위하여 버퍼 회로(B) 및 저역 통과 회로(C3)가 제공된다.
Abstract:
A transmitter system comprises an oscillator and having an adjustable monolithic capacitor circuit used for frequency stabilization. The oscillator signal is modulated and transmitted. A data generating chip is coupled to the transmitter. The data generating chip is used for adjusting and controlling the transmitter oscillator frequency signal. The adjustable capacitor circuit is located internal to the data generating chip and is coupled to a ground pin and one of a plurality of function pins on the data generating chip. The adjustable capacitor circuit is used for adjusting and setting the centerpoint of the transmitter oscillator frequency signal.
Abstract:
A low noise linear amplifier and a microwave voltage controlled oscillator constructed from such amplifier. Each amplifier within the VCO utilizes a ratioed transistor configuration to generate a linear output over a wide range of inputs. Output current from the amplifier is split into a main output current and components of in-phase and 180 DEG out-of-phase current. A logarithmic tuning control combines the components of in-phase and 180 DEG out-of-phase currents in inverse ratio to provide a constant d.c. feedback current.
Abstract:
An oscillator which is easily formed into an integrated circuit and stably operated and the oscillation frequency of which can be adjusted within a wide range. The oscillator has two phase shifting circuits (10C and 30C) and a feedback resistor (70). The phase shifting circuits (10C and 30C) each have an operational amplifier which receives signals through a resistor at an inverting input terminal, a series circuit comprising a capacitor across both ends of which the voltage of the input signal is applied and a variable resistor, and a resistor for feeding back the output of the operational amplifier to the inverting input terminals. The output of the phase shifting circuit (10C) is connected to the input of the phase shifting circuit (30C). The feedback resistor (70) feeds back the signal outputted from the phase shifting circuit (30C) to the input side of the phase shifting circuit (10C).
Abstract:
A phase-locked-loop circuit includes an oscillator having R-C networks that are coupled to a positive feedback path of the oscillator. An amplifier having a controllable gain is included in the positive feedback path. Variation of the gain of the amplifier produces a corresponding variation in the frequency of the oscillator. A pair of differentially symmetrical signals are produced in the positive feedback path and combined in a differential amplifier to form an oscillatory signal.
Abstract:
An oscillator (100, 200) and a method of adjusting the frequency of oscillation of the oscillator (100, 200) are disclosed for generating a signal with an adjustable frequency in a frequency range from 1GHz to 200GHz. The oscillator (100, 200) includes a loop circuit. The loop circuit has an amplifier (101), a delay element or filter (103), a phase shifter (102), a device for adjusting the phase shifter (102), and a coupler (104) to provide an output signal. The adjusting device is coupled to the phase shifter (102).
Abstract:
A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.
Abstract:
A frequency detector of a phase-lock-loop circuit is used for measuring a frequency error between a frequency of an output signal of an oscillator and a frequency of a synchronizing signal. When the frequency error in each of 32 periods of the synchronizing signal exceeds a predetermined magnitude, the phase-lock-loop circuits begins operating in a coarse frequency correction mode. As long as the 32 periods have not lapsed, the phase-lock-loop circuit operates in an idle mode of operation and the oscillator is not corrected. As a result, during vertical retrace, when equalizing pulses occur, the phase-lock-loop circuit is not disturbed by a large frequency error.