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公开(公告)号：US09820073B1
公开(公告)日：2017-11-14
申请号：US15591549
申请日：2017-05-10
Applicant: TLS Corp.
Inventor： Frank Foti
CPC classification number: H04S5/005 , H03G3/3005 , H03G3/301 , H03G5/165 , H03G9/025 , H03G2201/106 , H04S2400/05 , H04S2400/07
Abstract: Extracting a common signal from multiple audio signals may include summing a first signal and a second signal to obtain a first+second signal; subtracting the second signal from the first signal to obtain a first−second signal; transforming the first+second signal and the first−second signal to frequency domain representations; calculating absolute value of the frequency domain representations of the first+second signal and the first−second signal; subtracting the absolute value of the frequency domain representation of the first−second signal from the absolute value of the frequency domain representation of the first+second signal to obtain a difference signal; multiplying the difference signal by the frequency domain representation of the first+second signal to obtain a product signal; dividing the product signal by the absolute value of the frequency domain representation of the first+second signal to obtain a frequency domain representation of the common signal; and transforming the frequency domain representation to the common signal.
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公开(公告)号：US09490755B2
公开(公告)日：2016-11-08
申请号：US15184910
申请日：2016-06-16
Applicant: Freescale Semiconductor, Inc.
Inventor： Abdulrhman M. S. Ahmed , Mario M. Bokatius , Paul R. Hart , Joseph Staudinger , Richard E. Sweeney
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
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33.发明申请公开(公告)号：US20140253248A1
公开(公告)日：2014-09-11
申请号：US14287139
申请日：2014-05-26
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： ABDULRHMAN M.S. AHMED , MARIO M. BOKATIUS , PAUL R. HART , JOSEPH STAUDINGER , RICHARD E. SWEENEY
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first series circuit and a second series circuit in parallel with the first series circuit. The first series circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first adjustable attenuator series coupled between the first input and the first output. The second series circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter and a second adjustable attenuator series coupled between the second input and the second output.
Abstract translation: 与包括多个放大器路径的放大器一起使用的电路的实施例包括与第一串联电路并联的第一串联电路和第二串联电路。 第一串联电路包括耦合到第一功率分配器输出的第一输入，耦合到多个放大器路径的第一放大器路径的第一输出，以及耦合在第一输入和第二输出之间的第一可调移相器和第一可调衰减器 第一输出。 第二串联电路包括耦合到第二功率分配器输出的第二输入，耦合到多个放大器路径的第二放大器路径的第二输出以及耦合在第二输入和第二输入之间的第二可调移相器和第二可调衰减器串联 第二输出。
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公开(公告)号：US08736347B2
公开(公告)日：2014-05-27
申请号：US13959254
申请日：2013-08-05
Applicant: Freescale Semiconductor, Inc.
Inventor： Abdulrhman M. S. Ahmed , Mario M. Bokatius , Paul R. Hart , Joseph Staudinger , Richard E. Sweeney
IPC: G06G7/12
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the first and second adjustable phase shifters and attenuation levels to be applied by the first and second adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the first and second adjustable phase shifters and the first and second adjustable attenuators.
Abstract translation: 可调功率分配器包括：具有输入的功率分配器和第一和第二分频器输出; 第一可调移相器和第一可调衰减器串联耦合到第一分频器输出并提供第一功率输出; 第二可调移相器和第二可调衰减器串联耦合到第二分频器输出并提供第二功率输出; 界面; 和控制器。 控制器被配置为经由接口接收指示要由第一和第二可调移相器施加的相移的数据和由第一和第二可调衰减器施加的衰减电平，并且基于该数据来控制 由第一和第二可调移相器以及第一和第二可调衰减器施加的相移和衰减电平。
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公开(公告)号：US11784735B2
公开(公告)日：2023-10-10
申请号：US17719300
申请日：2022-04-12
Applicant: Wilson Electronics, LLC
Inventor： Joshua Kent Barnes , Christopher Ken Ashworth
IPC: H04B7/14 , H04B17/40 , H04B17/327 , H04B17/336 , H03G3/30 , H04B7/15
CPC classification number: H04B17/40 , H03G3/3042 , H04B7/15 , H04B17/327 , H04B17/336 , H03G2201/103 , H03G2201/106 , H03G2201/307
Abstract: A technology is described for adjusting repeater gain based on user equipment need. A downlink path of the repeater can be deactivated. A deactivated throughput value can be received from the UE for data received at the UE in a selected time period. The downlink amplification path of the repeater can be activated. An activated throughput value for data received at the UE in the selected time period can be received from the UE. A difference can be determined between the deactivated throughput value and the activated throughput value. A repeater gain value can be reduced or bypassed when the deactivated throughput value is greater than the activated throughput value by a selected threshold value.
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Patent Agency Ranking
公开(公告)号：US11752356B2
公开(公告)日：2023-09-12
申请号：US16273519
申请日：2019-02-12
Applicant: NeuroEM Therapeutics, Inc.
Inventor： Gary W. Arendash , Rob Baranowski
CPC classification number: A61N1/40 , A61N1/0476 , A61N5/04 , H03G3/30 , H03G3/3036 , H03G3/3042 , H01Q1/273 , H03G2201/103 , H03G2201/106 , H03G2201/307
Abstract: In one example in accordance with the present disclosure, an antenna system is described. The antenna system includes an array of antennas. Each antenna emits electromagnetic waves and is presented with a load that is different from other antennas in the array. The antenna system also includes a control system. The control system includes a single transmitter to sequentially drive antenna sets, a switching device to select, for each activation period in an activation sequence, an antenna set to be driven, and a controller. The controller determines an actual power output of each antenna and generates an adjusted control signal for the single transmitter such that the output of each antenna is controlled to match a target power for that antenna, regardless of a load for the antenna.
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公开(公告)号：US11699979B2
公开(公告)日：2023-07-11
申请号：US17515464
申请日：2021-10-30
Applicant: Biamp Systems, LLC
Inventor： Aaron Faulstich
CPC classification number: H03F1/3264 , G10L25/21 , H03G3/3005 , H03G11/008 , H04R3/007 , H04R3/02 , H04R3/04 , H03G2201/106
Abstract: Example embodiments provide a process that includes one or more of receiving an audio signal at a feedback compressor circuit, multiplying the received audio signal with a power feedback signal to create a product audio signal, wherein the feedback signal comprises a low-pass filtered signal, applying a power amplifier to the product audio signal, and providing the amplified product audio signal as an output signal to a speaker.
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公开(公告)号：US20180175807A1
公开(公告)日：2018-06-21
申请号：US15895863
申请日：2018-02-13
Applicant: pSemi Corporation
Inventor： Hossein Noori , Chih-Chieh Cheng
CPC classification number: H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
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公开(公告)号：US20180159480A1
公开(公告)日：2018-06-07
申请号：US15874740
申请日：2018-01-18
Applicant: NXP USA, Inc.
Inventor： ABDULRHMAN M.S. AHMED , MARIO M. BOKATIUS , PAUL R. HART , JOSEPH STAUDINGER , RICHARD E. SWEENEY
IPC: H03F1/02 , H04L27/22 , G06F13/42 , H04L7/00 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/21 , H03F3/60 , H03G1/00 , H03F3/68
CPC classification number: H03F1/0288 , G06F13/4282 , G06G7/10 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/602 , H03F3/68 , H03F2200/387 , H03F2200/438 , H03F2200/451 , H03F2203/21106 , H03F2203/21193 , H03G1/0088 , H03G2201/106 , H04L7/0079 , H04L27/22
Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.
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公开(公告)号：US09991852B2
公开(公告)日：2018-06-05
申请号：US15528934
申请日：2015-11-02
Applicant: ICEpower a/s
Inventor： Kennet Skov Andersen
CPC classification number: H03F1/305 , H03F1/02 , H03F3/183 , H03F3/187 , H03F3/217 , H03F3/2173 , H03F2200/03 , H03F2200/129 , H03F2200/135 , H03F2200/144 , H03F2200/156 , H03F2200/258 , H03F2200/342 , H03F2200/426 , H03F2200/441 , H03F2200/444 , H03F2200/66 , H03F2200/78 , H03G3/301 , H03G3/348 , H03G2201/106
Abstract: A close-down pop reduction system and a method for close-down pop reduction in an audio amplifier assembly are disclosed. The switching power conversion system comprises a forward path having a compensator and a switching power stage and a signal path from an output of a comparator in the switching power stage to a sequence control unit. The signal path includes a close-down timing circuit configured to provide a timing signal. The sequence control unit is configured to eliminate the input signal, increase the switch frequency of the close-down pop reduction system and disable the switching power stage at a moment in time within a PWM pulse of the switching power stage. Hereby, it is e.g. possible to minimize the audible pop during close-down of audio amplifier assemblies.
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