公开(公告)号：JPS5780952U

公开(公告)日：1982-05-19

申请号：JP15495980

申请日：1980-10-31

IPC: H04L1/00 ,  G06F3/00 ,  G06F11/00 ,  G06F11/10 ,  G06F11/30 ,  G06F13/00 ,  H04L11/00 ,  G06F3/04 ,  H04L1/10

公开(公告)号：JPS56161736A

公开(公告)日：1981-12-12

申请号：JP6445680

申请日：1980-05-15

Applicant: NIPPON ELECTRIC CO

Inventor： HASHIBA HIDEYASU

IPC: H03M13/27 ,  H04L1/00 ,  H04L1/10

Abstract: PURPOSE:To reduce the redundancy without lowering the entire error correcting ability and to increase the transmitting efficiency, by using two types of an error correction code and an error detection code for a code train, and correcting the error in the error detection code by the error correction code. CONSTITUTION:Data inputted from an input terminal 1 is separated into two code groups at a distribution circuit 2, a redundant code is added with an error correction code forming circuit 3 and an error detection code forming circuit 4, respectively and the output of the circuits 3, 4 is alternately located at a synthesis circuit 5, and after it is stored at an interleave circuit 6, it is read out in the different order and transmitted to a line 7. At the reception side, the reception data is returned to the original order at an interleave circuit 8, it is separated into two code groups at a distribution circuit 9, the code group using the error correction code is corrected at an error correction circuit 10, and the information indicating the location of error is transmitted to a burst location judging circuit 12. The code group using the error detection code detects error at an error detection circuit 11, the circuit 12 judges the location and length of the burst and corrects the bit in error in the error detection code.

公开(公告)号：JPS56147638U

公开(公告)日：1981-11-06

申请号：JP4571880

申请日：1980-04-03

IPC: G06F11/10 ,  G06F11/00 ,  H03M13/00 ,  H04L1/10

公开(公告)号：JPS56140915U

公开(公告)日：1981-10-24

申请号：JP3874680

申请日：1980-03-26

IPC: G06F11/10 ,  G06F11/08 ,  G11B5/09 ,  G11B20/18 ,  H03M5/04 ,  H03M13/27 ,  H04B1/10 ,  H04B14/04 ,  H04N5/92 ,  H04N5/93 ,  H04B12/02 ,  H04L1/10 ,  H04L3/02

公开(公告)号：JPS55133659U

公开(公告)日：1980-09-22

申请号：JP3177079

申请日：1979-03-14

IPC: G11B20/18 ,  G11B5/09 ,  H03M13/27 ,  H04B14/04 ,  H04N5/93 ,  H04L1/10 ,  H04B12/02

公开(公告)号：JPS55120251A

公开(公告)日：1980-09-16

申请号：JP2734579

申请日：1979-03-09

Applicant: MEIDENSHA ELECTRIC MFG CO LTD

Inventor： UCHIUMI HIROAKI ,  AOKI KIYOSHI

IPC: H03M13/00 ,  H04J3/14 ,  H04L1/00 ,  H04L1/10

Abstract: PURPOSE:To prevent a composite word from being processed as error data even when a transmission error occurs, by adding an error flag to word data. CONSTITUTION:Receiving signal SR is code-decided 11 and the decision result is inputted to parity check part 12, shift register 13 and synchronizing word detection part 15. The output of register 13 is supplied to double-transmission collation part 16 and colated there with the output of bit counter 14 and when collation is completed, its output is supplied to error proceesing part 17. Then, the existenece of a parity check NG flag is formed under the condition of counter 14 and stored in memory 18. The existence of this flag is set on each word unit of frame constitution. At transfer timing determined by the cndition of counter 14, output data of register 13 and the flag of memory 18 are coupled 19 and supplied to external unit 20.

公开(公告)号：JPS5591251U

公开(公告)日：1980-06-24

申请号：JP17450578

申请日：1978-12-19

IPC: H03M5/04 ,  H03M13/51 ,  H04L1/10 ,  G06F5/02

公开(公告)号：JPS5557851U

公开(公告)日：1980-04-19

申请号：JP14065678

申请日：1978-10-12

IPC: G06F11/08 ,  G06F11/10 ,  H03M13/00 ,  H04L1/10

公开(公告)号：JPS5513460B2

公开(公告)日：1980-04-09

申请号：JP104474

申请日：1973-12-30

IPC: H03M13/00 ,  G06F3/00 ,  G06F11/08 ,  G06F11/10 ,  H04L1/10

公开(公告)号：JPS5429630U

公开(公告)日：1979-02-27

申请号：JP10184577

申请日：1977-08-01

IPC: H04L1/00 ,  G06F7/00 ,  G06F11/00 ,  H03K19/00 ,  H04Q9/00 ,  H04Q9/14 ,  H04L1/10