公开(公告)号：US20110198694A1

公开(公告)日：2011-08-18

申请号：US12707150

申请日：2010-02-17

Applicant: Man Fai NG ,  Bin YANG

Inventor： Man Fai NG ,  Bin YANG

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/76267 ,  H01L21/823878 ,  H01L29/66772

Abstract: Methods and devices are provided for fabricating a semiconductor device having barrier regions within regions of insulating material resulting in outgassing paths from the regions of insulating material. A method comprises forming a barrier region within an insulating material proximate the isolated region of semiconductor material and forming a gate structure overlying the isolated region of semiconductor material. The barrier region is adjacent to the isolated region of semiconductor material, resulting in an outgassing path within the insulating material.

Abstract translation: 提供了用于制造在绝缘材料区域内具有阻挡区域的半导体器件的方法和装置，导致从绝缘材料区域的脱气路径。 一种方法包括在靠近半导体材料的隔离区域的绝缘材料内形成阻挡区域，并形成覆盖半导体材料的隔离区域的栅极结构。 阻挡区域与半导体材料的隔离区域相邻，导致绝缘材料内的除气路径。

公开(公告)号：US07994014B2

公开(公告)日：2011-08-09

申请号：US12249570

申请日：2008-10-10

Applicant: Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

Inventor： Frank Bin Yang ,  Rohit Pal ,  Michael J. Hargrove

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02636 ,  H01L29/045 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: The disclosed subject matter relates to semiconductor transistor devices and associated fabrication techniques that can be utilized to form silicide contacts having an increased effective size, relative to conventional silicide contacts. A semiconductor device fabricated in accordance with the processes disclosed herein includes a layer of semiconductor material and a gate structure overlying the layer of semiconductor material. A channel region is formed in the layer of semiconductor material, the channel region underlying the gate structure. The semiconductor device also includes source and drain regions in the layer of semiconductor material, wherein the channel region is located between the source and drain regions. Moreover, the semiconductor device includes facet-shaped silicide contact areas overlying the source and drain regions.

Abstract translation: 所公开的主题涉及半导体晶体管器件和相关的制造技术，其可以用于形成相对于常规硅化物触点具有增加的有效尺寸的硅化物触点。 根据本文公开的方法制造的半导体器件包括覆盖半导体材料层的半导体材料层和栅极结构。 沟道区形成在半导体材料层中，栅极结构下方的沟道区。 半导体器件还包括半导体材料层中的源区和漏区，其中沟道区位于源区和漏区之间。 此外，半导体器件包括覆盖源极和漏极区域的面形硅化物接触区域。

公开(公告)号：US07981903B2

公开(公告)日：2011-07-19

申请号：US12671960

申请日：2008-08-06

Applicant: Stanley Dawes Chamberlain ,  Felix Deanda, Jr. ,  Roseanne Gerding ,  Masaichi Hasegawa ,  Kevin Kuntz ,  Huangshu Lei ,  Yasushi Miyazaki ,  Naohiko Nishigaki ,  Samarjit Patnaik ,  Aniko Redman ,  John Brad Shotwell ,  Kirk Stevens ,  Joseph Wilson ,  Bin Yang

Inventor： Stanley Dawes Chamberlain ,  Felix Deanda, Jr. ,  Roseanne Gerding ,  Masaichi Hasegawa ,  Kevin Kuntz ,  Huangshu Lei ,  Yasushi Miyazaki ,  Naohiko Nishigaki ,  Samarjit Patnaik ,  Aniko Redman ,  John Brad Shotwell ,  Kirk Stevens ,  Joseph Wilson ,  Bin Yang

IPC: A01N43/90 ,  A61K31/519 ,  C07D487/00

CPC classification number: C07D487/04 ,  C07D487/14

Abstract: Novel pyrrolopyrimidines as shown in formula (I): and pharmaceutically acceptable derivatives thereof. The compounds are useful in the inhibition of IGF-1R.

Abstract translation: 式（I）所示的新型吡咯并嘧啶及其药学上可接受的衍生物。 该化合物可用于抑制IGF-1R。

公开(公告)号：US07939852B2

公开(公告)日：2011-05-10

申请号：US12176835

申请日：2008-07-21

Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

IPC: H01L31/0328

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

公开(公告)号：US20110090773A1

公开(公告)日：2011-04-21

申请号：US12854145

申请日：2010-08-10

Applicant: Chih-Ching Yu ,  Pi-Hai Liu ,  Yu-Hsuan Lin ,  Ying-Feng Huang ,  Yuh Cheng ,  Jin-Bin Yang

Inventor： Chih-Ching Yu ,  Pi-Hai Liu ,  Yu-Hsuan Lin ,  Ying-Feng Huang ,  Yuh Cheng ,  Jin-Bin Yang

IPC: G11B20/10

CPC classification number: G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10296 ,  G11B20/1037 ,  G11B20/10425 ,  G11B2220/2537

Abstract: An apparatus for generating Viterbi-processed data using an input signal obtained from reading an optical disc includes a Viterbi decoding unit and a control circuit. The Viterbi decoding unit is arranged to process the input signal and generate the Viterbi-processed data. In addition, the control circuit is arranged to control at least one component of the apparatus based upon at least one signal within the apparatus. Additionally, the component includes a phase locked loop (PLL) processing unit, an equalizer, and/or the Viterbi decoding unit. An associated apparatus including an equalizer and a Viterbi module is further provided. An associated apparatus including a Viterbi decoding unit and a control circuit is also provided. An associated apparatus including an equalizer, at least one offset/gain controller, and a Viterbi module is further provided. An associated apparatus including an equalizer, a Viterbi module, and a peak/bottom/central (PK/BM/DC) detector is also provided.

Abstract translation: 使用从读取光盘获得的输入信号来产生维特比处理数据的装置包括维特比解码单元和控制电路。 维特比解码单元被布置成处理输入信号并生成维特比处理的数据。 此外，控制电路被布置成基于装置内的至少一个信号来控制装置的至少一个部件。 此外，该组件包括锁相环（PLL）处理单元，均衡器和/或维特比解码单元。 还提供了包括均衡器和维特比模块的相关设备。 还提供了包括维特比解码单元和控制电路的相关设备。 还提供了包括均衡器，至少一个偏移/增益控制器和维特比模块的相关设备。 还提供了包括均衡器，维特比模块和峰值/底部/中央（PK / BM / DC）检测器的相关设备。

公开(公告)号：US07928020B2

公开(公告)日：2011-04-19

申请号：US11862865

申请日：2007-09-27

Applicant: Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

Inventor： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. Alex See ,  Meisheng Zhou ,  Liang Choo Hsia

IPC: H01L21/00

CPC classification number: H01L21/3143 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

Abstract: A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

Abstract translation: 一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。 通过施加氮等离子体将氮引入到氧化硅层中。 在施加氮等离子体之后，将氧化硅层退火。 重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。 在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。 还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。

公开(公告)号：US20110024841A1

公开(公告)日：2011-02-03

申请号：US12904662

申请日：2010-10-14

Applicant: Frank Bin YANG ,  Andrew M. WAITE ,  Scott LUNING

Inventor： Frank Bin YANG ,  Andrew M. WAITE ,  Scott LUNING

IPC: H01L29/78 ,  H01L25/07

CPC classification number: H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

Abstract: A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

Abstract translation: 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：USD627499S1

公开(公告)日：2010-11-16

申请号：US29346994

申请日：2009-11-10

Applicant: Chi-Chung Hu ,  Zheng-Jay Huang ,  Yu-Pin Liu ,  Hong-Bin Yang

Designer： Chi-Chung Hu ,  Zheng-Jay Huang ,  Yu-Pin Liu ,  Hong-Bin Yang

公开(公告)号：US20100258198A1

公开(公告)日：2010-10-14

申请号：US12652027

申请日：2010-01-04

Applicant: Anna Lee Tonkovich ,  Bin Yang ,  Steven T. Perry ,  Sean P. Fitzgerald ,  Ravi Arora ,  Robert Luzenski ,  Thomas D. Yuschak

Inventor： Anna Lee Tonkovich ,  Bin Yang ,  Steven T. Perry ,  Sean P. Fitzgerald ,  Ravi Arora ,  Robert Luzenski ,  Thomas D. Yuschak

IPC: G05D7/01 ,  E04F13/072

CPC classification number: F28F13/06 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00822 ,  B01J2219/00824 ,  B01J2219/00833 ,  B01J2219/00835 ,  B01J2219/0086 ,  B01J2219/00889 ,  B01J2219/00891 ,  B01J2219/00995 ,  B01L3/502746 ,  B01L2200/027 ,  B01L2300/0864 ,  B01L2300/0887 ,  B01L2400/0487 ,  B01L2400/086 ,  F28F2260/02 ,  Y10T137/0396

Abstract: The invention provides apparatuses and techniques for controlling flow between a manifold and two or more connecting microchannels. Flow between plural connecting microchannels, that share a common manifold, can be made more uniform by the use of flow straighteners and distributors that equalize flow in connecting channels. Alternatively, flow can be made more uniform by sections of narrowed diameter within the channels. Methods of making apparatus and methods of conducting unit operations in connecting channels are also described.

Abstract translation: 本发明提供用于控制歧管和两个或更多个连接微通道之间的流动的装置和技术。 通过使用均衡连接通道中的流动的流平衡器和分配器，可以使共享共同歧管的多个连接微通道之间的流动更均匀。 或者，可以通过通道内的变窄直径的部分使流动更均匀。 还描述了在连接通道中进行单元操作的装置和方法的方法。

公开(公告)号：US20100233654A1

公开(公告)日：2010-09-16

申请号：US12681824

申请日：2008-10-08

Applicant: Ki Bin Yang

Inventor： Ki Bin Yang

IPC: A61C8/00

CPC classification number: A61C8/008 ,  A61C8/005

Abstract: A button for an implant healing abutment includes a button body coupled to an implant healing abutment; and a pressing part projecting sideward from the button body, wherein the pressing part covers, fixes and heals an incised gingival flap including attached gingiva. An implant healing abutment having a pressing part includes an implant healing abutment joined to an implant fixture; and a pressing part projecting sideward from the implant healing abutment, wherein the pressing part covers, fixes and heals an incised gingival flap including attached gingiva.

Abstract translation: 用于植入物愈合基台的按钮包括联接到植入物愈合基台的按钮体; 以及从按钮体侧向突出的按压部，其中，所述按压部覆盖，固定和愈合包括附接的牙龈的切开的牙龈瓣。 具有按压部分的植入愈合基台包括接合到植入物夹具的植入愈合基台; 以及从所述植入物愈合基台侧向突出的按压部，其中所述按压部覆盖，固定和愈合包括附接的牙龈的切开的牙龈瓣。